Quad 2-input NAND gate
INTEGRATED CIRCUITS
74F00 Quad 2-input NAND gate
Product specification IC15 Data Handbook 1990 Oct 04
Philips Semicond...
Description
INTEGRATED CIRCUITS
74F00 Quad 2-input NAND gate
Product specification IC15 Data Handbook 1990 Oct 04
Philips Semiconductors
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74F00
FEATURE
Industrial temperature range available (–40°C to +85°C)
TYPE TYPICAL PROPAGATION DELAY 3.4ns TYPICAL SUPPLY CURRENT (TOTAL) 4.4mA
PIN CONFIGURATION
D0a D0b Q0 D1a D1b Q1 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC D3b D3a Q3 D2b D2a Q2
74F00
SF00001
ORDERING INFORMATION
ORDER CODE DESCRIPTION 14-pin plastic DIP 14-pin plastic SO COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F00N N74F00D INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = –40°C to +85°C I74F00N I74F00D PKG DWG # SOT27-1 SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS Dna, Dnb Data inputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 LOAD VALUE HIGH/LOW 20µA/0.6mA 1.0mA/20mA
Qn Data output 50/33 NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
LOGIC DIAGRAM
D0a D0b D1a D1b D2a D2b VCC = Pin 14 GND = Pin 7 D3a D3b 1 2 4 5 9 10 12 13 11 3 Q0
FUNCTION TABLE
INPUTS Dna L L
8 Q2
OUTPUT Dnb L H L Qn H H H L
6
Q1
H
Q3
SF00002
H H NOTES: H = High voltage level L = Low voltage level
LOGIC SYMBOL
IEC/IEEE SYMBOL
1 1 2 4 5 9 10 12 13 2
&
3
4 6 D0a D0bD1a D1b D2a D2b D3a D3b 5
9 Q0 Q1 Q2 Q3 8 10
12 3 VCC = Pin 14 GND = Pin 7 6 8 11 11 13
SF00003
SF00004
October 4, 1990
2
853-0325 00623
Philips Semiconductors
Product specification
Quad 2-i...
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