Document
INTEGRATED CIRCUITS
74ALVT16601 18-bit universal bus transceiver (3-State)
Product specification Supersedes data of 1996 Nov 14 IC23 Data Handbook 1998 Feb 13
Philips Semiconductors
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit universal bus transceiver (3-State)
74ALVT16601
FEATURES
• 18-bit bidirectional bus interface • 5V I/O Compatible • 3-State buffers • Output capability: +64mA/-32mA • TTL input and output switching levels • Input and output interface capability to systems at 5V supply • Bus-hold data inputs eliminate the need for external pull-up • Live insertion/extraction permitted • Power-up reset • Power-up 3-State • No bus current loading when output is tied to 5V bus • Positive edge triggered clock inputs • Latch-up protection exceeds 500mA per JEDEC Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model resistors to hold unused inputs
DESCRIPTION
The 74ALVT16601 is a high-performance BiCMOS product designed for VCC operation at 2.5V and 3.3V with I/O compatibility up to 5V. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CPAB. When OEAB is Low, the outputs are active. When OEAB is High, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CEBA/CEAB). Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN CI/O ICCZ PARAMETER Propagation delay An to Bn or Bn to An Input capacitance (Control pins) I/O pin capacitance Total supply current CL = 50pF VI = 0V or VCC Outputs disabled; VI/O = 0V or VCC Outputs disabled CONDITIONS Tamb = 25°C TYPICAL UNIT 2.5V 1.9 2.5 4 8 40 3.3V 1.5 1.9 4 8 60 ns pF pF µA
ORDERING INFORMATION
PACKAGES 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C OUTSIDE NORTH AMERICA 74ALVT16601 DL 74ALVT16601 DGG NORTH AMERICA AV16601 DL AV16601 DGG DWG NUMBER SOT371-1 SOT364-1
PIN DESCRIPTION
PIN NUMBER 1, 27 29, 56 2, 28 55,30 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 4, 11, 18, 25, 32, 39, 46, 53 7, 22, 35, 50 SYMBOL OEAB/OEBA CEBA/CEAB LEAB/LEBA CPAB/CPBA A0-A17 B0-B17 GND VCC NAME AND FUNCTION A-to-B/ B-to-A Output enable input (active Low) B-to-A/A-to-B clock enable A-to-B/B-to-A Latch enable input A-to-B/B-to-A Clock input (active rising edge) Data inputs/outputs (A side) Data inputs/outputs (B side) Ground (0V) Positive supply voltage
1998 Feb 13
2
853-1885 18958
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit universal bus transceiver (3-State)
74ALVT16601
PIN CONFIGURATION
OEAB LEAB A0 GND A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND A12 A13 A14 VCC A15 A16 GND A17 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CEAB CPAB B0 GND B1 B2 VCC B3 B4 B5 GND B6 B7 B8 B9 B10 B11 GND B12 B13 B14 VCC B15 B16 GND B17 CPBA CEBA
FUNCTION TABLE
INPUTS CEAB X X X H L L L L X= H= L= ↑= Z= †= OEAB H L L L L L L L LEAB X H H L L L L L CPAB X X X X ↑ ↑ H L A X L H X L H X X OUTPUT B Z L H BO L H BO BO§
Don’t care High voltage level Low voltage level Low to High High impedance “off ” state A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CPBA, and CEBA. = Output level before the indicated steady-state input conditions were established. § = Output level before the indicated steady-state input conditions were established, provided that CPAB was Low before LEAB went Low.
SW00192
1998 Feb 13
3
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit universal bus transceiver (3-State)
74ALVT16601
LOGIC SYMBOL (Positive Logic)
OEAB 1
CEAB
56
CPAB
55
LEAB
2
LEBA
28
CPBA
30
CEBA
29
OEBA
27 CE
A0
3
ID C1 CLK CE ID C1 CLK
54
B0
To 17 other channels
SW00193
ABSOLUTE MAXIMUM RATINGS 1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 Output in Off or High state Output in Low state DC output out ut current Output in High state Storage temperature range –64 –65 to +150 °C VI < 0 CONDITIONS RATING –0.5 to +4.6 –50 –0.5 to +7.0 –50 –0.5 to +7.0 128 mA UNIT V mA V mA V
DC output diode current DC output voltage3
NOTES:.