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74ALVCH16240 Dataheets PDF



Part Number 74ALVCH16240
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Low Voltage 16-Bit Inverting Buffer/Line Driver
Datasheet 74ALVCH16240 Datasheet74ALVCH16240 Datasheet (PDF)

74ALVCH16240 Low Voltage 16-Bit Inverting Buffer/Line Driver September 2001 Revised February 2002 74ALVCH16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with Bushold General Description The ALVCH16240 contains sixteen inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit .

  74ALVCH16240   74ALVCH16240



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74ALVCH16240 Low Voltage 16-Bit Inverting Buffer/Line Driver September 2001 Revised February 2002 74ALVCH16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with Bushold General Description The ALVCH16240 contains sixteen inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The ALVCH16240 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating inputs at a valid logic level. The 74ALVCH16240 is designed for low voltage (1.65V to 3.6V) VCC applications with output capability up to 3.6V. The 74ALVCH16240 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Features s 1.65V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminates the need for external pull-up/pull-down resistors s tPD 3.9 ns max for 3.0V to 3.6V VCC 5.3 ns max for 2.3V to 2.7V VCC 6.0 ns max for 1.65V to 1.95V VCC s Uses patented noise/EMI reduction circuitry s Latch-up conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model > 200V Ordering Code: Order Number 74ALVCH16240T Package Number MTD48 Package Descriptions 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names OEn I0–I15 O0–O15 Description Output Enable Input (Active LOW) Bushold Inputs Outputs © 2002 Fairchild Semiconductor Corporation DS500629 www.fairchildsemi.com 74ALVCH16240 Connection Diagram Truth Tables Inputs OE1 L L H Inputs OE2 L L H Inputs OE3 L L H Inputs OE4 L L H I12–I15 L H X I8–I11 L H X I4–I7 L H X Outputs O8–O11 H L Z Outputs O12–O15 H L Z I0–I3 L H X Outputs O4–O7 H L Z Outputs O0–O3 H L Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance Functional Description The 74ALVCH16240 contains sixteen inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full 16-bit operation.The 3-STATE outputs are controlled by an Output Enable (OEn) input. When OEn is LOW, the outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the inputs. Logic Diagram www.fairchildsemi.com 2 74ALVCH16240 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) (Note 2) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V DC Output Source/.


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