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74AHC74 Dataheets PDF



Part Number 74AHC74
Manufacturers NXP
Logo NXP
Description Dual D-type flip-flop
Datasheet 74AHC74 Datasheet74AHC74 Datasheet (PDF)

INTEGRATED CIRCUITS DATA SHEET 74AHC74; 74AHCT74 Dual D-type flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1999 Aug 05 File under Integrated Circuits, IC06 1999 Sep 23 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V • Balanced propagation delays • Inputs accepts voltages higher than VCC • Fo.

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INTEGRATED CIRCUITS DATA SHEET 74AHC74; 74AHCT74 Dual D-type flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1999 Aug 05 File under Integrated Circuits, IC06 1999 Sep 23 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V • Balanced propagation delays • Inputs accepts voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Output capability: standard • ICC category: flip-flops • Specified from −40 to +85 and +125 °C. DESCRIPTION The 74AHC/AHCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT74 dual positive-edge triggered, D-type flip-flops with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. fmax CI CPD QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. 74AHC74; 74AHCT74 TYPICAL SYMBOL tPHL/tPLH PARAMETER propagation delay nCP to nQ, nQ nSD, nRD to nQ, nQ max. clock frequency input capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC AHCT CL = 15 pF; VCC = 5 V 3.7 3.7 130 VI = VCC or GND 4.0 12 3.3 3.7 100 4.0 16 ns ns MHz pF pF UNIT Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. FUNCTION TABLES Table 1 See note 1 INPUT nSD L H L Table 2 nRD H L L See note 1 INPUT nSD H H nRD H H nCP ↑ ↑ nD L H OUTPUT nQn+1 L H nQn+1 H L nCP X X X nD X X X nQ H L H OUTPUT nQ L H H Note to Tables 1 and 2 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH CP transition; Qn+1 = state after the next LOW-to-HIGH CP transition. 1999 Sep 23 2 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger ORDERING INFORMATION OUTSIDE NORTH AMERICA 74AHC74D 74AHC74PW 74AHCT74D 74AHCT74PW PINNING PIN 1 and 13 2 and 12 3 and 11 4 and 10 5 and 9 6 and 8 7 14 SYMBOL 1RD and 2RD 1D and 2D 1CP and 2CP 1SD and 2SD 1Q and 2Q 1Q and 2Q GND VCC data inputs 74AHC74; 74AHCT74 PACKAGE NORTH AMERICA 74AHC74D 74AHC74PW DH 74AHCT74D 74AHCT74PW DH TEMPERATURE RANGE −40 to +85 °C PINS 14 14 14 14 PACKAGE SO TSSOP SO TSSOP MATERIAL plastic plastic plastic plastic CODE SOT108-1 SOT402-1 SOT108-1 SOT402-1 DESCRIPTION asynchronous reset-direct input (active LOW) clock input (LOW-to-HIGH, edge-triggered) asynchronous set-direct input (active LOW) true flip-flop outputs complement flip-flop outputs ground (0 V) DC supply voltage handbook, halfpage 1RD 1D 1CP 1SD 1Q 1Q GND 1 2 3 4 5 6 7 MNA417 14 VCC 13 2RD 12 2D handbook, halfpage 4 10 1SD 2SD 2 12 3 11 SD 1Q 1D Q D 2D 2Q 1CP CP 2CP FF 1Q Q 2Q RD 1RD 2RD 1 13 MNA418 5 9 74 11 2CP 10 2SD 9 2Q 6 8 8 2Q Fig.1 Pin configuration. Fig.2 Logic diagram. 1999 Sep 23 3 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74; 74AHCT74 handbook, halfpage 4 1SD SD D CP FF Q RD 1Q 6 Q 2 handbook, halfpage 1D 1CP 1Q 5 4 3 2 1 S C1 1D R 5 3 6 1 1RD 2SD 10 11 12 13 S C1 1D R MNA419 10 9 12 11 2D 2CP SD D CP FF Q RD Q 2Q 8 9 2Q 8 13 2RD MNA420 Fig.3 IEC logic symbol. Fig.4 Functional diagram. handbook, full pagewidth Q C C C C D C RD SD CP C C C C Q C MNA421 Fig.5 Logic diagram (one flip-flop). 1999 Sep 23 4 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL VCC VI VO Tamb PARAMETER DC supply voltage input voltage output voltage operating ambient temperature see DC and AC characteristics per device VCC = 5 V ±0.5 V CONDITIONS MIN. 2.0 0 0 −40 −40 74AHC74; 74AHCT74 74AHCT UNIT TYP. MAX. 5.0 − − +25 +25 − − 5.5 5.5 VCC +85 V V V °C TYP. MAX. MIN. 5.0 − − +25 +25 − − 5.5 5.5 VCC +85 4.5 0 0 −40 +125 −40 100 20 − − +125 °C − 20 ns/V tr,tf (∆t/∆f) input rise and fall rates VCC = 3.3 V ±0.3 V − − LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). S.


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