Document
BA7078AF/AS
Multimedia ICs
Synchronization signal processor for high definition displays
BA7078AF/AS
The BA7078AF is a synchronization signal processing LSI chip designed for multiscan high-definition displays. It generates a synchronization signal and clamp pulse for three types of input signals: separate synchronization, composite synchronization, and synchronization on video.
!Application CRT displays
!Features 1) Operates on a single 5V power supply, with low power consumption. 2) Synchronization signal existence and polarity detec-tion output. 3) Adjustable clamp pulse width, allowing for the selec-tion of front or back editing. 4) Vertical synchronization separation is based on hori-zontal frequency tracking, for separation starting at 1H. 5) Minimal attached components.
!Absolute maximum ratings (Ta = 25°C)
Parameter Power supply voltage Power dissipation Operating temperature Symbol VCC
∗1
Limits 7.0 450(BA7078AF) 600(BA7078AS) −25 to +75
∗2
Unit V mW °C °C
Pd Topr
−55 to +125 Tstg Storage temperature ∗1 Reduced by 4.5mW for each increase in Ta of 1°C over 25°C. ∗2 Reduced by 6.0mW for each increase in Ta of 1°C over 25°C.
!Recommended operating conditions (Ta = 25°C)
Parameter Power supply voltage Symbol VCC Min. 4.5 Typ. 5.0 Max. 5.5 Unit V
1/12
BA7078AF/AS
Multimedia ICs
!Block diagram
HSCTL
1
18
POLH
C / HSYNC IN
2
H SYNC DET.
17
EXIH
VIDEO IN
3 SYNC SEPA.
16
POLV
VSEPA
4
HOR. SYNC CONTROL V SYNC SEPA.
15
EXIV
VSYNC IN
5
14
Vcc
CVPOL
6 V SYNC DET.
13
HDRV
CVEXI
7
12
CLAMP
CPSEL
8
CLAMP PULSE GEN.
11
VDRV
GND
9
10
CPWID
2/12
BA7078AF/AS
Multimedia ICs
!Pin descriptions
Pin No. Pin name
Functions Used to select whether to output the VDRV section of the HDRV output signal. High : VDRV section of HDRV is output Low : VDRV section of HDRV is not output Input either the composite synchronization signal or the horizontal synchronization signal. Input is clamped, and is initiated by capacitor coupling. Inputs the SYNC ON VIDEO signal(green). Input is sink chip clamped. Input is initiated by capacitor coupling. Converts the horizontal synchronization signal frequency into a voltage. The voltage generated is proportional to the frequency of the horizontal synchronization signal. Attach a 0.56µF capacitor between the ground pins. Inputs the vertical synchronization signal. Integrates the vertical synchronization signal polarity detection circuit. Attach a 1.5µF capacitor between this pin and the ground. Integrates the vertical synchronization signal existence detection circuit. Attach a 1µF capacitor between this pin and the ground. Used to set the clamp pulse generation position to either the front or back edge of HSYNC High : The front edge is the generation position Open : Composite / H SYNC IN : The front edge is the generation position VIDEO IN : The back edge is the generation position Low : The back edge is the generation position − Sets the clamp pulse width according to the attached time constant. Attach a resistor between this pin and VCC and, a capacitor between this pin and GND. When R = 3.9kΩ and C = 100pF, pulse width is approximately 400 ns. Set the resistor to register an abnormality at 1kΩ. Outputs the vertical synchronization signal. The output signal has positive polarity. Outputs the clamp pulse generated from the vertical synchronization signal. The output signal has a positive polarity. Outputs the clamp pulse generated from the horizontal synchronization signal. The output signal has positive polarity. − Indecates whether the vertical synchronization signal exists. For the output logic, refer to the separate table. Indicates the polarity of the vertical synchronization signal. For the output logic, refer to the separate table. Indicates whether the horizontal synchronization signal exists. For the output logic, refer to the separate table. Indicates the polarity of the horizontal synchronization signal. For the output logic, refer to the separate table.
1
HSCTL
HDRV output
2
C / HSYNC IN
Composite sync / H SYNC input SYNC ON VIDEO input
3
VIDEO IN
4
VSEPA
f-V conversion
5 6 7
VSYNC IN CVPOL CVEXI
V SYNC input Vertical polarity integration Vertical existence integration
8
CPSEL
Setting the clamp position
9
GND
Ground
10
CPWID
Setting the clamp pulse width
11 12 13 14 15 16 17 18
VDRV CLAMP HDRV VCC EXIV POLV EXIH POLH
VDRV output Clamp output HDRV output Power supply Vertical existence output Vertical polarity output Horizontal existence output Horizontal polarity output
3/12
BA7078AF/AS
Multimedia ICs
!Input / output circuits
HSCTL
VSEPA
C / HSYNC IN
VCC
VCC
VCC 670Ω
60kΩ
51kΩ 1pin
1kΩ 4pin
200Ω 2pin
30kΩ
10µA
VSYNC IN
VCC
VIDEO IN
VCC 2kΩ
CVPOL
VCC
200Ω
5pin
200Ω 6pin
3pin
CVEXI
VCC
CPWID
VCC
CPSEL
VCC
50kΩ
1kΩ
7pin
10pin
8pin
50kΩ
4/12
BA7078AF/AS
Multimedia ICs
VDRV
GND
CLAMP
VCC
VCC
9pin
12pin
11pin
HDRV
VCC
POLV
VCC
VCC
VCC
10kΩ
13pin
16pin
14pin
EXIH
VCC
EXIV
VC.