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EB03 Dataheets PDF



Part Number EB03
Manufacturers ETC
Logo ETC
Description TRIPLE INDEPENDENT LOGIC INTERFACED HALF BRIDGES
Datasheet EB03 DatasheetEB03 Datasheet (PDF)

TRIPLE INDEPENDENT LOGIC INTERFACED HALF BRIDGES EBO3 M I C R O T E C H N O L O G Y HTTP://WWW.APEXMICROTECH.COM (800) 546-APEX (800) 546-2739 FEATURES • • • • • COMPATIBLE WITH PWM FREQUENCIES UP TO 50KHZ 10V TO 200V MOTOR SUPPLY 5A CONTINUOUS OUTPUT CURRENT HCMOS COMPATIBLE SCHMITT TRIGGER LOGIC INPUTS SEPARATE SOURCE OUTPUTS FOR NEGATIVE RAIL CURRENT SENSE • SLEEP MODE • WIDE RANGE FOR GATE DRIVE AND LOGIC SUPPLIES APPLICATIONS HIGH POWER CIRCUITS FOR DIGITAL CONTROL OF: • THREE AXIS MO.

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TRIPLE INDEPENDENT LOGIC INTERFACED HALF BRIDGES EBO3 M I C R O T E C H N O L O G Y HTTP://WWW.APEXMICROTECH.COM (800) 546-APEX (800) 546-2739 FEATURES • • • • • COMPATIBLE WITH PWM FREQUENCIES UP TO 50KHZ 10V TO 200V MOTOR SUPPLY 5A CONTINUOUS OUTPUT CURRENT HCMOS COMPATIBLE SCHMITT TRIGGER LOGIC INPUTS SEPARATE SOURCE OUTPUTS FOR NEGATIVE RAIL CURRENT SENSE • SLEEP MODE • WIDE RANGE FOR GATE DRIVE AND LOGIC SUPPLIES APPLICATIONS HIGH POWER CIRCUITS FOR DIGITAL CONTROL OF: • THREE AXIS MOTION USING BRUSH TYPE MOTORS • THREE PHASE BRUSHLESS DC MOTOR DRIVE • THREE PHASE AC MOTOR DRIVE • THREE PHASE HIGH POWER MICROSTEPPING STEP MOTORS Hin 1 12 SD 11 Half Bridge Driver FET Half Bridge Output 13 14 HV1 OUT1 Lin 1 10 Vcc1 9 15 S1 HVRTN1 DESCRIPTION The EB03 consists of three independent FET half bridges with drivers. The drivers may be interfaced with CMOS or HCMOS level logic. 16 Hin 2 Vss,Logic Ground 8 17 Half Bridge Driver FET Half Bridge Output HV2 7 18 OUT2 Lin2 6 19 20 S2 HVRTN2 Vcc 2 5 Vdd,Logic Supply 4 Hin3 3 Half Bridge Driver Lin 3 2 FET Half Bridge Output 21 HV3 22 OUT3 23 24 S3 HVRTN3 Vcc 3 1 FIGURE 1. BLOCK DIAGRAM APEX MICROTECHNOLOGY CORPORATION • TELEPHONE (520) 690-8600 • FAX (520) 888-3329 • ORDERS (520) 690-8601 • EMAIL [email protected] 1 EB03 ABSOLUTE MAXIMUM RATINGS MOTOR VOLTAGE SUPPLY, HV OUTPUT CURRENT, peak OUTPUT CURRENT, continuous1 GATE SUPPLY VOLTAGE, Vcc LOGIC SUPPLY VOLTAGE, Vdd POWER DISSIPATION, internal1 LOGIC INPUT VOLTAGE THERMAL RESISTANCE TO CASE3 TEMPERATURE, pin solder, 10s TEMPERATURE, junction2 TEMPERATURE RANGE, storage OPERATING TEMPERATURE, case TEST CONDITIONS IOUT=5A; Vcc=10.8V, Vdd=5V; HV=100V, Fpwm=50kHz, L=100 µH " " " " " Set by external circuitry Set by internal resistors MIN 198.1 -1.7 TYP ABSOLUTE MAXIMUM RATINGS SPECIFICATIONS SPECIFICATIONS PARAMETER POSITIVE OUTPUT VOLTAGE NEGATIVE OUTPUT VOLTAGE POSITIVE EDGE DELAY RISETIME NEGATIVE EDGE DELAY FALLTIME PWM FREQUENCY INPUT IMPEDANCE 200V 10A 5A 20V 20V 40W -0.3V to Vdd + 0.3V 2.1°C/Watt 300°C 150°C –55 to +150°C –25 to +85°C MAX 201.9 1.9 310 50 290 50 50 50 UNITS Volts Volts n-second n-second n-second n-second kHz k-ohm INPUT AND OUTPUT SIGNALS PIN 1 2 3 4 5 6 7 8 9 10 11 12 NOTES: 1. 2. 3. SYMBOL Vcc3 Lin3 Hin3 Vdd Vcc2 Lin2 Vss Hin2 Vcc1 Lin1 SD Hin1 FUNCTION Gate supply 3 Low drive logic in 3 High drive logic in 3 Logic supply Gate supply 2 Low drive logic in 2 Signal ground High drive logic in 2 Gate supply 1 Low drive logic in 1 Shut down logic in High drive logic in 1 PIN 13 14 15 16 17 18 19 20 21 22 23 24 SYMBOL HV1 OUT1 S1 HVRTN1 HV2 OUT 2 S2 HVRTN2 HV3 OUT 3 S3 HVRTN 3 FUNCTION High Voltage supply 1 Section 1 output Section 1 source Section 1 return High voltage supply 2 Section 2 output Section 2 source Section 2 return High voltage supply 3 Section 3 output Section 3 source Section 3 return Over Entire Environmental Range. Long term operation at the maximum junction temperature will result in reduced product life. Lower internal temperature by reducing internal dissipation or using better heatsinking to achieve high MTTF. Each FET. INPUT A logic level input independently controls each FET in the half bridge. A logic level high turns on the FET and low turns it off. A common shut down input turns off all FETs when high. All inputs are Schmitt triggers with the upper threshold at 2/3 Vdd and the lower threshold at 1/3 Vdd. This comfortably interfaces with CMOS or HCMOS provided that the Vdd for the logic family and the EB03 are the same. TTL families may be used if a pull-up to Vcc is added to the TTL gates driving the EB03, and Vdd for the EB03 is the same supply as Vcc for the TTL family. An open signal connector pulls the shut down input high and all other inputs low, insuring that all outputs are off. However, input impedance is 50k on all inputs; therefore if one input is open circuited a high radiated noise level could spuriously turn on a FET. OUTPUT Each output section consists of a switching mode FET half bridge. Separate HV supply, emitter, and HV return lines are provided for each section. The FETs are conservatively rated to carry 5A. At 5A the saturation voltage is 1.9V maximum. Each FET has an intrinsic diode connected in anti-parallel. When switching an inductive load this diode will conduct, and the drop at 5A will be 1.9V maximum. APEX MICROTECHNOLOGY CORPORATION • 5980 NORTH SHANNON ROAD • TUCSON, ARIZONA 85741 • USA • APPLICATIONS HOTLINE: 1 (800) 546-2739 2 PACKAGE SPECIFICATIONS EB03 PACKAGE SPECIFICATIONS DIP9 PACKAGE WEIGHT: 69 g or 2.4 oz DIMENSIONS ARE IN INCHES ALTERNATE UNITS ARE [MM] APEX MICROTECHNOLOGY CORPORATION • TELEPHONE (520) 690-8600 • FAX (520) 888-3329 • ORDERS (520) 690-8601 • EMAIL [email protected] 3 OPERATING CONSIDERATIONS EB03 current. (The size of the antenna.) Therefore the 1µF ceramic capacitors should bypass each HV to its return right at the pins the EB03. POWER SUPPLY REQUIREM.


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