FAN1654

www.fairchildsemi.com FAN1654 1.5A LDO, DDR Bus Termination Regulator Features Sinks and sources 1A continuous, 1.5A peak -40°C to +125°C Operating Range Load regulation: (VDDQ/2) ± 40mV 5mA VREF buffer tracks VTT On-chip thermal limiting Power-enhanced eTSSOP™-16 package Low Current Shutdown Mode Output Short Circuit Protection Description The FAN1654 is a low-cost bi-directional LDO specifically designed for terminating DDR memory bus. It can both sink and source up to 1A continuous, 1.5A peak, providing enough current for most DDR applications. Load regulation meets the JEDEC spec, VTT = (VDDQ/2) ± 40mV. The FAN1654 includes a buffered reference voltage capable of supplying up to 5mA current. On-chip thermal limiting provides protection against a combination of power overload and ambient temperature that would create an excessive junction temperature. A shutdown input puts the FAN1654 into a low power mode for laptop computer applications. The FAN1654 regulator is available in a power-enhanced eTSSOP™-16 package, and the standard SOIC-14 Applications DDR terminators Block Diagram VDDQ 200k VREFOUT VREFIN + VTTFORCE + VTTFORCE 200k VTTSENSE FAN1655 VSSQ VSS VSS VSS VDD VDD VDD SHDN REV. 1.0.5 4/17/02 PRODUCT SPECIFICATION FAN1654 Pin Assignments VDD VDD VTTFORCE VSS VSS VTTFORCE VDD VSS 1 2 3 4 5 6 7 8 FAN1654 16 15 14 13 12 11 10 9 NC VDDQ VREFOUT VSSQ SHDN VREFIN VTTSENSE NC VSSQ VREFOUT VDDQ VDD VDD VTTFORCE VSS 1 2 3 4 5 6 7 FAN1654 14 13 12 1...