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F50N06LE Dataheets PDF



Part Number F50N06LE
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description 50A/ 60V/ 0.022 Ohm/ Logic Level N-Channel Power MOSFETs
Datasheet F50N06LE DatasheetF50N06LE Datasheet (PDF)

RFG50N06LE, RFP50N06LE, RF1S50N06LESM Data Sheet October 1999 File Number 4072.3 50A, 60V, 0.022 Ohm, Logic Level N-Channel Power MOSFETs These N-Channel enhancement mode power MOSFETs are manufactured using the latest manufacturing process technology. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, m.

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RFG50N06LE, RFP50N06LE, RF1S50N06LESM Data Sheet October 1999 File Number 4072.3 50A, 60V, 0.022 Ohm, Logic Level N-Channel Power MOSFETs These N-Channel enhancement mode power MOSFETs are manufactured using the latest manufacturing process technology. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA49164. Features • 50A, 60V • rDS(ON) = 0.022Ω • Temperature Compensating PSPICE® Model • Peak Current vs Pulse Width Curve • UIS Rating Curve • 175oC Operating Temperature • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Ordering Information PART NUMBER RFG50N06LE RFP50N06LE RF1S50N06LESM PACKAGE TO-247 TO-220AB TO-263AB BRAND FG50N06L FP50N06L F50N06LE Symbol D G NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in tape and reel, i.e. RF1S50N06LESM9A. S Packaging JEDEC STYLE TO-247 SOURCE DRAIN GATE DRAIN (BOTTOM SIDE METAL) DRAIN (FLANGE) JEDEC TO-220AB SOURCE DRAIN GATE JEDEC TO-263AB DRAIN (FLANGE) GATE SOURCE 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE® is a registered trademark of MicroSim Corporation. www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 RFG50N06LE, RFP50N06LE, RF1S50N06LESM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFG50N06LE, RFP50N06LE, RF1S50N06LESM 60 60 ±10 50 Refer to Peak Current Curve Refer to UIS Curve 142 0.95 -55 to 175 300 260 UNITS V V V A Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg W W/oC oC oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) CISS COSS CRSS RθJC RθJA TO-247 TO-220AB and TO-263AB VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 48V, ID = 50A, RL = 0.96Ω Figures 21, 21 TEST CONDITIONS ID = 250µA, VGS = 0V, Figure 13 VGS = VDS, ID = 250µA, Figure 12 VDS = 55V, VGS = 0V VDS = 50V, VGS = 0V, TC = 150oC VGS = ±10V ID = 50A, VGS = 5V, Figure 11 VDD = 30V, ID = 50A, RL = 0.6Ω, VGS = 5V, RGS = 2.5Ω Figures 10, 18, 19 MIN 60 1 TYP 20 170 48 90 96 57 2.2 2100 600 230 MAX 3 1 250 10 0.022 230 165 120 70 2.7 1.05 30 80 UNITS V V µA µA µA Ω ns ns ns ns ns ns nC nC nC pF pF pF oC/W oC/W oC/W Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient VDS = 25V, VGS = 0V, f = 1MHz Figure 14 Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Diode Reverse Recovery Time NOTES: 2. Pulse test: pulse width ≤ 80µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). SYMBOL VSD trr TEST CONDITIONS ISD = 45A ISD = 45A, dISD/dt = 100A/µs MIN .


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