March 1998
FDN357N N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
SuperSOTTM-3 N-Ch...
March 1998
FDN357N N-Channel Logic Level Enhancement Mode Field Effect
Transistor
General Description
SuperSOTTM-3 N-Channel logic level enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMCIA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package.
Features
1.9 A, 30 V, RDS(ON) = 0.090 Ω @ VGS = 4.5 V RDS(ON) = 0.060 Ω @ VGS = 10 V. Industry standard outline SOT-23 surface mount package using proprietary SuperSOTTM-3 design for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
SOIC-16
D
D
7 35
S
SuperSOT -3
TM
G
G
S
Absolute Maximum Ratings
Symbol VDSS VGSS ID PD TJ,TSTG RθJA RθJC Parameter Drain-Source Voltage
TA = 25oC unless other wise noted FDN357N 30 ±20 1.9 10
(Note 1a) (Note 1b)
Units V V A
Gate-Source Voltage - Continuous Drain/Output Current - Continuous - Pulsed Maximum Power Dissipation
0.5 0.46 -55 to 150
W
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Thermal Resistance...