FDG6302P

July 1999 FDG6302P Dual P-Channel, Digital FET General Description These dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Features -25 V, -0.14 A continuous, -0.4 A peak. RDS(ON) = 10 Ω @ VGS= -4.5 V, RDS(ON) = 13 Ω @ VGS= -2.7 V. Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1.5 V). Gate-Source Zener for ESD ruggedness (>6kV Human Body Model). Compact industry standard SC70-6 surface mount package. SC70-6 SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 D1 G2 S2 .02 G1 D2 1 or 4 * 6 or 3 2 or 5 5 or 2 . SC70-6 S1 3 or 6 4 or 1 * *The pinouts are symmetrical; pin 1 and 4 are interchangeable. Units inside the carrier can be of either orientation and will not affect the functionality of the device. Absolute Maximum Ratings Symbol Parameter TA = 25°C unless otherwise noted FDG6302P Units VDSS VGSS ID PD TJ,TSTG ESD Drain-Source Voltage Gate-Source Voltage Drain/Output Current - Continuous - Pulsed Maximum Power Dissipation (Note 1) -25 -8 -0.14 -0.4 0.3 -55 to 150 6.0 V V A W °C kV Operating and Storage Temperature Range Electrostatic Discharge Rating MIL-STD-883D Human Body Mode...