FDC6320C

October 1997 FDC6320C Dual N & P Channel , Digital FET General Description These dual N & P Channel logic level enhancement mode field effec transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. The device is an improved design especially for low voltage applications as a replacement for bipolar digital transistors in load switching applications. Since bias resistors are not required, this dual digital FET can replace several digital transistors with difference bias resistors. Features N-Ch 25 V, 0.22 A, RDS(ON) = 5 Ω @ VGS= 2.7 V. P-Ch 25 V, -0.12 A, RDS(ON) = 13 Ω @ VGS= -2.7 V. Very low level gate drive requirements allowing direct operation in 3 V circuits. VGS(th) < 1.5 V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model Replace NPN & PNP digital transistors. SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 4 3 5 2 6 1 Absolute Maximum Ratings Symbol VDSS, VCC VGSS, VIN ID, IO PD TJ,TSTG ESD Parameter TA = 25oC unless other wise noted N-Channel 25 8 P-Channel -25 -8 -0.12 -0.5 0.9 0.7 -55 to 150 6 °C kV W Units V V A Drain-Source Voltage, Power Supply Voltage Gate-Source Voltage, Drain/Output Current - Continuous - Pulsed Maximum Power Dissipation (Note 1a) (Note 1b) 0.22 0.5 Operating and Storage Tempature Ranger Electrostatic Discharge Rating MIL-STD-883D Human Body Model (100pf / 1500 Ohm) THERMAL CHARACTERIST...