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HSP50307 Dataheets PDF



Part Number HSP50307
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description Burst QPSK Modulator
Datasheet HSP50307 DatasheetHSP50307 Datasheet (PDF)

HSP50307 December 1996 Burst QPSK Modulator Description The HSP50307 is a mixed signal burst QPSK Modulator for upstream CATV Applications. The HSP50307 demultiplexes and modulates a serial data stream onto an RF Carrier centered between 8 and 15MHz. The signal spectrum is shaped with α = 0.5 root raised cosine (RRC) digital filters. On-chip filtering limits spurs and harmonics to levels below -35dBc during transmissions. The output power level is adjustable over a 40dB range in 1dB steps. The ma.

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HSP50307 December 1996 Burst QPSK Modulator Description The HSP50307 is a mixed signal burst QPSK Modulator for upstream CATV Applications. The HSP50307 demultiplexes and modulates a serial data stream onto an RF Carrier centered between 8 and 15MHz. The signal spectrum is shaped with α = 0.5 root raised cosine (RRC) digital filters. On-chip filtering limits spurs and harmonics to levels below -35dBc during transmissions. The output power level is adjustable over a 40dB range in 1dB steps. The maximum differential output level is +62dBmV into 75Ω . A transmitter inhibit function disables the RF output outside the burst interval. The differential output amplifier int7-erfaces to the cable via a transformer. The Block Diagram of the HSP50307 QPSK Modulator is shown below. The HSP50307 consists of a digital control interface, an I/Q generator, a synthesizer, and a quadrature modulator. The data clock is derived from the master clock. The HSP50307 demultiplexes the input data bits into in-phase (I) and quadrature (Q) data streams. The first bit and subsequent alternating bits of the burst are in-phase data. The two data streams are filtered, converted from digital to analog, and low pass filtered to produce the baseband I and Q analog signals. PKG. NO. M28.3 Features • 256 KBPS Data Rate and 128 KBPS Baud Rate • Burst QPSK Modulation • Programmable Carrier Frequency from 8MHz to 15MHz With a Frequency Step Size of 32kHz • α = 0.5 Root Raised Cosine (RRC) Filtering For Spectrum Shaping • On-Board Synthesizer • Programmable Output Level From 22 to 62dBmV in 1dB Steps • Programmable Charge Pump Current Control • 62dBmV Differential Output Driver for 75Ω Cable Applications • Burst QPSK Modulator • HSP50307EVAL1 Evaluation Board Is Available Ordering Information PART NUMBER HSP50307SC TEMP. RANGE (oC) 0 to 70 PACKAGE 28 Ld SOIC The baseband signals are up-converted to RF in the Quadrature Modulation Section. The synthesizer provides the local oscillator (LO) for the quadrature modulator. The frequency is programmable via the control interface with a resolution of 32kHz. The output of the quadrature modulator is low pass filtered to remove harmonic distortion. Block Diagram RCLK VCO_IN VCO_SET PD_OUT RESET CCLK C_EN CDATA TX_EN I TX_DATA DEMUX CONTROL INTERFACE SYNTHESIZER † QUAD GEN QUADRATURE MODULATOR † I/Q GENERATOR 9 8RRC D/A LPF † MOD_OUT+ LPF PGA MOD_OUT+ D/A LPF TX_EN Q 9 8RRC TXCLK MCLK /100 IBBIN QBBOUT † Indicates analog circuitry. MCLK MUST ALWAYS BE PRESENT FOR PROPER OPERATION IBBOUT QBBIN DAC_REF VCM_REF CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 4219 7-68 HSP50307 Pinout 28 LEAD SOIC TOP VIEW MCLK 1 TXCLK 2 TX_EN 3 TX_DATA 4 RESET 5 DGND 6 AVCC 7 AGND 8 IBBOUT 9 QBBOUT 10 QBBIN 11 IBBIN 12 DAC_REF 13 VCM_REF 14 28 CCLK 27 CDATA 26 C_EN 25 DVCC 24 RCLK 23 AGND 22 PD_OUT 21 VCO_IN 20 VCO_SET 19 AVCC 18 MOD_OUT17 MOD_OUT+ 16 AVDD 15 AGND Pin Description SYMBOL MCLK TXCLK TX_EN TYPE I O I Master clock input (25.6MHz). (D) PSK data clock (256kHz) for PSK_DATA_IN. (D) Transmit Enable. When high, the modulator output is enabled. This pin should be high for the entire burst. The signal is extended internally until data has fully exited the part before turning off for spurious free turn on and turn off. (D) 256 KBPS serial data input. (D) Digital Reset Pin (active low). The part is reset immediately on assertion of the reset pin. The output of the part is disabled on the assertion of reset. The part will come out of reset 2 master clock periods after the reset is deasserted. Reprogramming (see Control Interface Section) is needed after deassertion of reset for proper operation. (D) Negative supply for the digital filters and control. (P) Positive supply for the quadrature modulator. AVCC should be tied to +5V analog. (P) Negative supply for the quadrature modulator. AGND is tied to GND. (P) I baseband filtered output. (A) Q baseband filtered output. (A) Q baseband modulator input. (A) I baseband modulator input. (A) D/A reference node. A 0.1µF capacitor to ground is suggested. (A) Modulator common mode reference node. A 0.1µF capacitor to ground is suggested. (A) Negative supply for the cable interface. (P) Positive supply for the cable interface (+9V analog). (P) Positive output drive pin for the cable interface. (A) Negative output drive pin for the cable interface. (A) DESCRIPTION TX_DATA RESET I I DGND AVCC AGND IBBOUT QBBOUT QBBIN IBBIN DAC_REF VCM_REF AGND AVDD MOD_OUT+ MOD_OUT- I I I O O I I O O I I O O 7-69 HSP50307 Pin Description SYMBOL AVCC VCO_SET VCO_IN PD_OUT AGND RCLK DVCC C_EN CDATA CCLK TYPE I I/O I O I I I I I I (Continued) DESCRIPTION Positive supply for the synthesizer (+5V analog). (P) VCO free running frequency set resistor (normally 6.25kΩ). (D) Voltage-controlled oscillator control voltage. (D) Phase/frequency de.


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