AD9860

a Mixed-Signal Front-End (MxFE™) Processor for Broadband Communications AD9860/AD9862* FUNCTIONAL BLOCK DIAGRAM VIN+A VIN–A 1x PGA ADC BYPASSABLE LOW-PASS DECIMATION FILTER VIN+B VIN–B SIGDELT 1x PGA ADC RxB DATA [0:11] HILBERT FILTER RxA DATA [0:11] FEATURES Mixed-Signal Front-End Processor with Dual Converter Receive and Dual Converter Transmit Signal Paths Receive Signal Path Includes: Two 10-/12-Bit, 64 MSPS Sampling A/D Converters with Internal or External Independent References, Input Buffers, Programmable Gain Amplifiers, Low-Pass Decimation Filters, and a Digital Hilbert Filter Transmit Signal Path Includes: Two 12-/14-Bit, 128 MSPS D/A Converters with Programmable Full-Scale Output Current, Channel Independent Fine Gain and Offset Control, Digital Hilbert and Interpolation Filters, and Digitally Tunable Real or Complex Up-Converters Delay-Locked Loop Clock Multiplier and Integrated Timing Generation Circuitry Allow for Single Crystal or Clock Operation Programmable Output Clocks, Serial Programmable Interface, Programmable Sigma-Delta, Three Auxiliary DAC Outputs and Two Auxiliary ADCs with Dual Multiplexed Inputs APPLICATIONS Broadband Wireless Systems Fixed Wireless, WLAN, MMDS, LMDS Broadband Wireline Systems Cable Modems, VDSL, PowerPlug Digital Communications Set-Top Boxes, Data Modems GENERAL DESCRIPTION ⌺-⌬ LOGIC LOW AD9860/AD9862 SPI REGISTERS SPI INTERFACE AUX_DAC_A AUX_DAC_B AUX_DAC_C AUX DAC AUX DAC AUX DAC Rx PATH TIMING Tx PATH TIMING AUX ADC CLO...