Document
A428316 Series
Preliminary
Document Title 256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History
Rev. No.
0.0 0.1 0.2 0.3
256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
History
Initial issue Modify AC data Modify DC data and all parts guarantee self-refresh mode Delete -30,-40 grade and add -25 grade
Issue Date
June 13, 2001 April 26, 2002 June 10, 2002 August 20, 2002
Remark
Preliminary
PRELIMINARY
(August, 2002, Version 0.3)
AMIC Technology, Inc.
A428316 Series
Preliminary
Features
n Organization: 262,144 words X 16 bits n Part Identification - A428316 (512 Ref.) n Single 5.0V power supply/built-in VBB generator n Low power consumption - Operating: 110mA (-25 max) - Standby: 2.5mA (TTL), 1.0mA (CMOS) 1.0mA (Self-refresh current) n High speed - 25/35 ns RAS access time - 12/17 ns column address access time - 8/10 ns CAS access time - 12/16 ns EDO Page Mode Cycle Time n Industrial operating temperature range: -40°C to 85°C for -U n Fast Page Mode with Extended Data Out n Separate CAS ( UCAS , LCAS ) for byte selection n 512 Refresh Cycle in 8ms n Read-modify-write, RAS -only, CAS -before- RAS , Hidden refresh capability n TTL-compatible, three-state I/O n JEDEC standard packages - 400mil, 40-pin SOJ - 400mil, 40/44 TSOP type II package
256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
General Description
The A428316 is a new generation randomly accessed memory for graphics, organized in a 262,144-word by 16bit configuration. This product can execute Byte Write and Byte Read operation via two CAS pins. The A428316 offers an accelerated Fast Page Mode
This allow random access of up to 512 words within a row at a 83/62 MHz EDO cycle, making the A428316 ideally suited for graphics, digital signal processing and high performance computing systems.
Pin Descriptions
Symbol Description Address Inputs Data Input/Output Row Address Strobe Column Address Strobe for Lower Byte (I/O0 – I/O7) Column Address Strobe for Upper Byte (I/O8 – I/O15) WE OE VCC VSS NC Write Enable Output Enable 5.0V Power Supply Ground No Connection
Pin Configuration nSOJ
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
n TSOP
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
A0 – A8 I/O0 - I/O15 RAS
LCAS
UCAS
cycle with a feature called Extended Data Out (EDO).
PRELIMINARY
A428316S
(August, 2002, Version 0.3)
A428316V
1
AMIC Technology, Inc.
A428316 Series
Selection Guide
Symbol tRAC tAA tCAC tOEA tRC tPC Description Maximum RAS Access Time Maximum Column Address Access Time Maximum CAS Access Time Maximum Output Enable ( OE ) Access Time Minimum Read or Write Cycle Time Minimum EDO Cycle Time -25 25 12 8 8 44 12 -35 35 17 10 10 62 16 Unit ns ns ns ns ns ns
Functional Description
The A428316 reads and writes data by multiplexing an 18bit address into a 9-bit row and 9-bit column address. RAS and CAS are used to strobe the row address and the column address, respectively. The A428316 has two CAS inputs: LCAS controls I/O0I/O7, and UCAS controls I/O8 - I/O15, UCAS and LCAS function in an identical manner to CAS in that either will generate an internal CAS signal. The CAS function and timing are determined by the first CAS ( UCAS or LCAS ) to transition low and by the last to transition high. Byte Read and Byte Write are controlled by using LCAS and UCAS separately. A Read cycle is performed by holding the WE signal high during RAS / CAS operation. A Write cycle is executed by holding the WE signal low during RAS / CAS operation; the input data is latched by the falling edge of WE or CAS , whichever occurs later. The data inputs and outputs are routed through 16 common I/O pins, with RAS , CAS , WE and OE controlling the in direction. EDO Page Mode operation all 512 columns within a selected row to be randomly accessed at a high data rate. A EDO Page Mode cycle is initiated with a row address latched by RAS followed by a column address latched by CAS . While holding RAS low, CAS can be toggled to strobe changing column addresses, thus achieving shorter cycle times. The A428316 offers an accelerated Fast Page Mode cycle through a feature called Extended Data Out, which keeps the output drivers on during the CAS precharge time (tcp). Since data can be output after CAS goes high, the user is not required to wait for valid data to appear before starting the next access cycle. Data-out will remain valid as long as RAS and OE are low, and WE is high; this is the only characteristic which differentiates Extended Data Out operation from a standard Read or Fast Page Read. A me.