A26E001A

A26E001A 2M and 256K MaskRAM Document Title 2M and 256K MaskRAM Revision History Rev. No. 2.0 2.1 History Final spec release Change tOE speed from 150ns to 200ns Issue Date October 12, 1998 November 20, 1998 Remark Final (November, 1998, Version 2.1) AMIC Technology, Inc. A26E001A 2M and 256K MaskRAM Features n Power supply range: 1.8V to 3.3V n Access time: 450 ns (max.) n Current: Low power version: Operating: 4mA (max.) Standby: 10µA (max.) n Extended operating temperature range: -25° C to 85° C n n n n n Full static operation, no clock or refreshing required All inputs and outputs are CMOS compatible Common I/O using three-state output Data retention voltage: 1.6V (min.) Available in 32-pin TSOP and sTSOP packages General Description The A26E001A is a low operating current 262,144 x 8 bit CMOS MASK ROM and 32,768 x 8 bit CMOS SRAM integrated into one chip. It operates on a low power supply voltage from 1.8V to 3.3V, with two chip selects to enable the MASK ROM or SRAM independently. Inputs and three-state outputs are CMOS compatible and allow for direct interfacing with common system bus structures. Minimum standby power is drawn by this device when ROMCE and RAMCE are at a high level, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 1.6V. Pin Configuration Pin Description ~ ~ ~ ~ A11 A9 A8 A13 A14 A17 RAMCE VCC WE A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A26E001AV 32 31 30 29 28 2...