ACS112MS

ACS112MS January 1996 Radiation Hardened Dual J-K Flip-Flop Pinouts 16 PIN CERAMIC DUAL-IN-LINE MIL-STD-1835, DESIGNATOR CDIP2-T16, LEAD FINISH C TOP VIEW CP1 1 K1 2 J1 3 S1 4 16 VCC 15 R1 14 R2 13 CP2 12 K2 11 J2 10 S2 9 Q2 Features Devices QML Qualified in Accordance with MIL-PRF-38535 Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96704 and Intersil’sIntersil QM Plan 1.25 Micron Radiation Hardened SOS CMOS Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si) Single Event Upset (SEU) Immunity: <1 x 10 (Typ) -10 Errors/Bit/Day MEV-cm2/mg SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 Dose Rate Upset . . . . . . . . . . . . . . . . >10 11 Q1 5 Q1 6 Q2 7 GND 8 RAD (Si)/s, 20ns Pulse Dose Rate Survivability . . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse Latch-Up Free Under Any Conditions Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC Significant Power Reduction Compared to ALSTTL Logic DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min Input Current ≤ 1µA at VOL, VOH Fast Propagation Delay . . . . . . . . . . . . . . . . 21ns (Max), 14ns (Typ) 16 PIN CERAMIC FLATPACK MIL-STD-1835, DESIGNATOR CDFP4-F16, LEAD FINISH C TOP VIEW CP1 K1 J1 S1 Q1 Q1 Q2 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC R1 R2 CP2 K2 J2 S2 Q2 Description The...