Document
A67L83161/A67L83181/ A67L73321/A67L73361 Series
256K X 16/18, 128K X 32/36 Preliminary
Document Title 256K X 16/18, 128K X 32/36 LVTTL, Flow-through DBATM SRAM Revision History
Rev. No. 0.0
0.1
LVTTL, Flow-through DBATM SRAM
History
Initial issue Change fast access time from 7.5/8.0/8.5/9.0 ns to 10/11/12 ns Change set-up time from 2.0/2.2/2.5 ns to 2.5 ns Fix pin assignment error for pin 14 and pin 16
Issue Date
April 7, 1999 September 15, 1999
Remark
Preliminary
PRELIMINARY
(September, 1999, Version 0.1)
AMIC Technology, Inc.
DBA and Direct Bus Alternation are trademarks of AMIC Technology, Inc
A67L83161/A67L83181/ A67L73321/A67L73361 Series
256K X 16/18, 128K X 32/36 Preliminary
Features
n Fast access time: 10/11/12 ns (100, 90, 83 MHz) n Direct Bus Alternation between READ and WRITE cycles allows 100% bus utilization n Signal +3.3V ± 5% power supply n Individual Byte Write control capability n Clock enable ( CEN ) pin to enable clock and suspend operations n Clock-controlled and registered address, data and control signals n Registered output for pipelined applications n Three separate chip enables allow wide range of options for CE control, address pipelining n Internally self-timed write cycle n Selectable BURST mode (Linear or Interleaved) n SLEEP mode (ZZ pin) provided n Available in 100 pin LQFP package
LVTTL, Flow-through DBATM SRAM
General Description
The AMIC Direct Bus Alternation™ (DBA™) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L83161, A67L83181, A67L73321, A67L73361 SRAMs integrate a 256K X 16, 256K X 18, 128K X 32 or 128K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during WriteRead alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. The synchronous inputs include all address, all data inputs, active low chip enable ( CE ), two additional chip enables for easy depth expansion (CE2, CE2 ), cycle start input (ADV/LD ), synchronous clock enable ( CEN ), byte write enables ( BW1, BW2 , BW3 , BW4 ) and read/write (R/ W ). Asynchronous inputs include the output enable ( OE ), clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and burst mode (MODE). Burst Mode can provide either interleaved or linear operation, burst operation can be initiated by synchronous address Advance/Load (ADV/LD ) pin in Low state. Subsequent burst address can be internally generated by the chip and controlled by the same input pin ADV/LD in High state. Write cycles are internally self-time and synchronous with the rising edge of the clock input and when R/ W is Low. The feature simplified the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/Oa pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins; and BW4 controls I/Od pins. Cycle types can only be defined when an address is loaded, i.e., when ADV/LD is LOW. Parity/ECC bits are only available on the X18/36 version. The SRAM operates from a +3.3V power supply, and all inputs and outputs are LVTTL-compatible. The device is ideally suited for high bandwidth utilization systems.
PRELIMINARY
(September, 1999, Version 0.1)
1
AMIC Technology, Inc.
DBA and Direct Bus Alternation are trademarks of AMIC Technology, Inc
A67L83161/A67L83181/ A67L73321/A67L73361 Series
Pin Configuration
OE ADV/ LD
BW4
BW3
BW2
BW1
VCC
CEN
VSS
CLK
CE2
CE2
R/W
128K X 36/32
CE A6 A7
NC
NC
A8 A8 82
BW2
BW1
CEN
OE ADV/ LD
VCC
VSS
CLK
CE2
CE2
R/W
NC
NC
NC
NC
CE
256K X 18/16
A6 A7
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
I/Oc0 /NC I/Oc1 I/Oc2 VCCQ VSSQ I/Oc3 I/Oc4 I/Oc5 I/Oc6 VSSQ VCCQ I/Oc7 I/Oc8 VSS VCC VCC VSS I/Od 0 I/Od 1 VCCQ VSSQ I/Od 2 I/Od 3 I/Od 4 I/Od 5 VSSQ VCCQ I/Od6 I/Od7 I/Od 8/NC
NC NC NC VCCQ VSSQ NC NC I/Ob0 I/Ob1 VSSQ VCCQ I/Ob 2 I/Ob3 VSS VCC VCC VSS I/Ob 4 I/Ob 5 VCCQ VSSQ I/Ob6 I/Ob7 I/Ob8/NC NC VSSQ VCCQ NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100
81 80 79 78 77 76 75 74 73 72 71 70 69
A9
A9
A17 NC NC VCCQ VSSQ NC I/Oa 8 /NC I/Oa 7 I/Oa 6 VSSQ VCCQ I/Oa 5 I/Oa 4 VSS VSS VCC ZZ I/Oa 3 I/Oa 2 VCCQ VSSQ I/Oa 1 I/Oa 0 NC NC VSSQ VCCQ NC NC NC
I/Ob8 /NC I/Ob7 I/Ob6 VCCQ VSSQ I/Ob5 I/Ob4 I/Ob3 I/Ob2 VSSQ VCCQ I/Ob1 I/Ob0 VSS VSS VCC ZZ I/Oa8 I/Oa7 VCCQ VSSQ I/Oa6 I/Oa5 I/Oa4 I/Oa3 VSSQ VCCQ I/Oa2 I/Oa1 I/Oa0/ NC
A67L83161E A67L83181E A67L73321E A67L73361E
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
MODE MODE
A10
A11
A12
A13
A14
A15 A15
VSS
VCC
A10
A1
A11
A12
A13
A14
VSS
VCC
A16
A5
A4
A3
A2
A0
NC
NC
NC
NC
A16
A5
A4
A3
A2
A1
A0
NC
NC
NC
NC
PRELIMINARY
(September, 1999, Version 0.1)
2
AMIC Technology, Inc.
A67L83161/A67L83181/ A67L73321/A67L7.