ACT-D1M96S

ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module Features I I I I I I I I 6 Low Power Micron 1M X 16 Synchronous Dynamic Random Access Memory Chips in one MCM User Configureable as "2" Independent 512K X 48 X 2 Banks High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface 3.3-V Power Supply (±10% Tolerance) Separate Logic and Output Driver Power Pins Two Banks for On-Chip Interleaving (Gapless Accesses) Up to 50-MHz Data Rates CAS Latency (CL) Programmable to 2 Cycles From Column-Address Entry I I I I I I I I Burst Length Programmable to 4 or 8 Pipeline Architecture Cycle-by-Cycle DQ-Bus Write Mask Capability With Upper and Lower Byte Control Chip Select and Clock Enable for Enhanced-System Interfacing Serial Burst Sequence Auto-Refresh 4K Refresh (Total for Both Banks) 200-lead CQFP, cavity-up package General Description The ACT-D1M96S device is a high-speed 96Mbit synchronous dynamic random access memory (SDRAM) organized as 2 independent 512K X 48 X 2 banks. All inputs and outputs of the ACT-D1M96S are compatible with the LVTTL interface. All inputs and outputs are synchronized with the CLK input to simplify system design and enhance use with high-speed microprocessors and caches. BLOCK DIAGRAM CS1 CLK1 CKE1 DQMU1 DQML1 RAS1 CAS1 WE1 A0-A11 BANK T BANK B 16 16 16 S E C T I O N A 12 1M X 16 or 512K X 16 X 2 Banks 1M X 16 or 512K X 16 X 2 Banks 1M X 16 or 512K X 16 X 2 Banks DQ 0-15 CS2 CLK2 CKE2 DQMU2 DQML2 RAS2 CAS2 WE2 BA0-BA11 BANK...