Document
a
FEATURES 12.5 MHz Master Clock Frequency 0 V to +2.5 V or ؎ 1.25 V Input Range Single Bit Output Stream 90 dB Dynamic Range Power Supplies: AVDD, DVDD: +5 V ؎ 5% On-Chip 2.5 V Voltage Reference 28-Lead TSSOP
CMOS Sigma-Delta Modulator AD7720
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DVDD DGND REF1
AD7720
2.5V REFERENCE
REF2
VIN(+) VIN(–)
SIGMA-DELTA MODULATOR
DATA SCLK
MZERO GC
CLOCK CIRCUITRY
XTAL1/MCLK XTAL2
BIP
CONTROL LOGIC
DVAL RESETO RESET
STBY
GENERAL DESCRIPTION
This device is a 7th order sigma-delta modulator that converts the analog input signal into a high speed 1-bit data stream. The part operates from a +5 V supply and accepts a differential input range of 0 V to +2.5 V or ± 1.25 V centered about a commonmode bias. The analog input is continuously sampled by the analog modulator, eliminating the need for external sample and hold circuitry. The input information is contained in the output stream as a density of ones. The original information can be reconstructed with an appropriate digital filter. The part provides an accurate on-chip 2.5 V reference. A reference input/output function is provided to allow either the internal reference or an external system reference to be used as the reference source for the part. The device is offered in a 28-lead TSSOP package and designed to operate from –40°C to +85°C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1997
AD7720–SPECIFICATIONS1 REF2 = +2.5 V; T = T
Parameter STATIC PERFORMANCE Resolution Differential Nonlinearity Integral Nonlinearity Precalibration Offset Error Precalibration Gain Error2 Postcalibration Offset Error3 Postcalibration Gain Error2, 3 Offset Error Drift Gain Error Drift Unipolar Mode Bipolar Mode ANALOG INPUTS Signal Input Span (VIN(+) – VIN(–)) Bipolar Mode Unipolar Mode Maximum Input Voltage Minimum Input Voltage Input Sampling Capacitance Input Sampling Rate Differential Input Impedance REFERENCE INPUTS REF1 Output Voltage REF1 Output Voltage Drift REF1 Output Impedance Reference Buffer Offset Voltage Using Internal Reference REF2 Output Voltage REF2 Output Voltage Drift Using External Reference REF2 Input Impedance External Reference Voltage Range DYNAMIC SPECIFICATIONS4 Bipolar Mode Signal to (Noise + Distortion)5 Total Harmonic Distortion5 Spurious Free Dynamic Range Unipolar Mode Signal to (Noise + Distortion)5 Total Harmonic Distortion5 Spurious Free Dynamic Range Intermodulation Distortion AC CMRR Overall Digital Filter Response 0 kHz–90.625 kHz 96.92 kHz 104.6875 kHz to 12.395 MHz CLOCK MCLK Duty Ratio VMCLKH, MCLK High Voltage VMCLKL, MCLK Low Voltage 90 86/84.5 –90/–88 –90 88 84.5/83 –89/–87 –90 –93 96 ± 0.005 –3 90 45 to 55 4 0.4 dB typ dB min dB max dB max dB typ dB min dB max dB max dB typ dB typ B Version 16 ±1 ±2 ±6 ± 0.6 ± 1.5 ± 0.3 ±1 ±1 ± 0.5 Units Bits LSB max LSB typ mV typ % FSR typ mV typ % FSR typ LSB/°C typ LSB/°C typ LSB/°C typ
(AVDD = +5 V ؎ 5%; DVDD = +5 V ؎ 5%; AGND = DGND = 0 V, fMCLK = 12.5 MHz, A MIN to TMIN, unless otherwise noted)
Test Conditions/Comments When Tested with Ideal FIR Filter as in Figure 1 Guaranteed Monotonic
REF2 Is an Ideal Reference, REF1 = AGND
± VREF2/2 0 to VREF2 AVDD 0 2 2 fMCLK 109/(8 fMCLK) 2.32 to 2.62 60 3 ± 12 2.32 to 2.62 60 109/(16 fMCLK) 2.32 to 2.62
V max V max V V pF typ MHz kΩ typ V min/max ppm/°C typ kΩ typ mV max V min/max ppm/°C typ kΩ typ V min/max
BIP = VIH BIP = VIL
Offset Between REF1 and REF2
REF1 = AGND Applied to REF1 or REF2 When Tested with Ideal FIR Filter as in Figure 1 BIP = VIH, VCM = 2.5 V, VIN(+) = VIN(–) = 1.25 V p-p or VIN(–) = 1.25 V, VIN(+) = 0 V to 2.5 V Input BW = 0 kHz–90.625 kHz Input BW = 0 kHz–90.625 kHz Input BW = 0 kHz–90.625 kHz BIP = VIL, VIN(–) = 0 V, VIN(+) = 0 V to 2.5 V Input BW = 0 kHz–90.625 kHz Input BW = 0 kHz–97.65 kHz Input BW = 0 kHz–97.65 kHz VIN(+) = VIN(–) = 2.5 V p-p, VCM = 1.25 V to 3.75 V, 20 kHz See Figure 1 for Characteristics of FIR Filter
dB max dB min dB typ % max V min V max For Specified Operation MCLK Uses CMOS Logic
–2–
REV. 0
AD7720
Parameter LOGIC INPUTS VIH, Input High Voltage VIL, Input Low Voltage IINH, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD IDD (Total for AVDD, DVDD) Active Mode Standby Mode B Version 2 0.8 10 10 2.4 0.4 4.75/5.25 4.75/5.25 43 25 Units V min V max µA max pF max V min V max V min/V max V min/V max Digital Inputs Equal to 0 V or DVDD mA max µA max |IOUT| ≤ 200 µA |IOUT| ≤ 1.6 mA Test Conditions/Comments
.