DatasheetsPDF.com

SAML11E14 Dataheets PDF



Part Number SAML11E14
Manufacturers Microchip
Logo Microchip
Description Ultra Low-Power 32-bit Cortex-M23 MCUs
Datasheet SAML11E14 DatasheetSAML11E14 Datasheet (PDF)

Ultra Low-Power, 32-bit Cortex-M23 MCUs with TrustZone, Crypto, and Enhanced PTC SAM L10/L11 Family Features • Operating Conditions: 1.62V to 3.63V, -40ºC to +125ºC, DC to 32 MHz • Core: 32 MHz (2.64 CoreMark/MHz and up to 31 DMIPS) Arm® Cortex®-M23 with: – Single-cycle hardware multiplier – Hardware divider – Nested Vector Interrupt Controller (NVIC) – Memory Protection Unit (MPU) – Stack Limit Checking – TrustZone® for ARMv8-M (optional) • System – Power-on Reset (POR) and programmable Brown-o.

  SAML11E14   SAML11E14



Document
Ultra Low-Power, 32-bit Cortex-M23 MCUs with TrustZone, Crypto, and Enhanced PTC SAM L10/L11 Family Features • Operating Conditions: 1.62V to 3.63V, -40ºC to +125ºC, DC to 32 MHz • Core: 32 MHz (2.64 CoreMark/MHz and up to 31 DMIPS) Arm® Cortex®-M23 with: – Single-cycle hardware multiplier – Hardware divider – Nested Vector Interrupt Controller (NVIC) – Memory Protection Unit (MPU) – Stack Limit Checking – TrustZone® for ARMv8-M (optional) • System – Power-on Reset (POR) and programmable Brown-out Detection (BOD) – 8-channel Direct Memory Access Controller (DMAC) – 8-channel event system for Inter-peripheral Core-independent Operation – CRC-32 generator • Memory – 16/32/64-KB Flash – 4/8/16-KB SRAM – 2-KB Data Flash Write-While-Read (WWR) section for non-volatile data storage – 256 bytes TrustRAM with physical protection features • Clock Management – Flexible clock distribution optimized for low power – 32.768 kHz crystal oscillator – 32.768 kHz ultra low-power internal RC oscillator – 0.4 to 32 MHz crystal oscillator – 16/12/8/4 MHz low-power internal RC oscillator – Ultra low-power digital Frequency-Locked Loop (DFLLULP) – 32-96 MHz fractional digital Phase-Locked Loop (FDPLL96M) – One frequency meter • Low-Power and Power Management – Active, Idle, Standby with partial or full SRAM retention and off sleep modes: • Active mode (< 25 μA/MHz) • Idle mode (< 10 μA/MHz) with 1.5 μs wake-up time • Standby with Full SRAM Retention (0.5 μA) with 5.3 μs wake-up time • Off mode (< 100 nA) Data Sheet © 2023 Microchip Technology Inc. and its subsidiaries DS60001513J - 1 SAM L10/L11 Family – Static and dynamic power gating architecture – Sleepwalking peripherals – Two performance levels – Embedded Buck/LDO regulator with on-the-fly selection • Security – Up to four tamper pins for static and dynamic intrusion detections – Data Flash • Optimized for secure storage • Address and data scrambling with user-defined key (optional) • Rapid tamper erase on scrambling key and on one user-defined row • Silent access for data read noise reduction – TrustRAM • Address and data scrambling with user-defined key • Chip-level tamper detection on physical RAM to resist microprobing attacks • Rapid tamper erase on scrambling key and RAM data • Silent access for data read noise reduction • Data remanence prevention – Peripherals • One True Random Generator (TRNG) • AES-128, SHA-256, and GCM cryptography accelerators (optional) • Secure pin multiplexing to isolate on dedicated I/O pins a secured communication with external devices from the non-secure application (optional) – TrustZone for flexible hardware isolation of memories and peripherals (optional) • Up to six regions for the Flash • Up to two regions for the Data Flash • Up to two regions for the SRAM • Individual security attribution for each peripheral, I/O, external interrupt line, and Event System Channel – Secure Boot with SHA-based authentication (optional) – Up to three debug access levels – Up to three Chip E.


SAML11D16 SAML11E14 SAML11E15


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)