524S

Low Skew 1 to 4 Clock Buffer 524S DATASHEET Description The 524S is a low skew, single input to four output, clock buffer. The 524S has best in class additive phase Jitter of sub 50 fsec. IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact us for all of your clocking needs. Features Low additive phase jitter RMS: 50fs Extremely low skew outputs (50ps) Low cost clock buffer Packaged in 8-pin SOIC and 8-pin DFN, Pb-free Input/Output clock frequency up to 200 MHz Non-inverting output clock Ideal for networking clocks Operating Voltages: 1.8V to 3.3V Advanced, low power CMOS process Extended temperature range (-40°C to +105°C) Block Diagram ICLK Q0 Q1 Q2 Q3 524S REVISION A 03/18/15 1 ©2015 Integrated Device Technology, Inc. 524S DATASHEET Pin Assignments ICLK Q0 Q1 NC 1 2 3 4 8 GND 7 Q3 6 Q2 5 VDD 8-pin SOIC ICLK Q0 Q1 NC 1 2 3 4 8 GND 7 Q3 6 Q2 5 VDD 8-pin DFN...