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TPN1200APL Dataheets PDF



Part Number TPN1200APL
Manufacturers Toshiba
Logo Toshiba
Description Silicon N-channel MOSFET
Datasheet TPN1200APL DatasheetTPN1200APL Datasheet (PDF)

MOSFETs Silicon N-channel MOS (U-MOS-H) TPN1200APL 1. Applications • High-Efficiency DC-DC Converters • Switching Voltage Regulators • Motor Drivers 2. Features (1) High-speed switching (2) Small gate charge: QSW = 7.5 nC (typ.) (3) Small output charge: Qoss = 24 nC (typ.) (4) Low drain-source on-resistance: RDS(ON) = 9.8 mΩ (typ.) (VGS = 10 V) (5) Low leakage current: IDSS = 10 µA (max) (VDS = 100 V) (6) Enhancement mode: Vth = 1.5 to 2.5 V (VDS = 10 V, ID = 0.3 mA) 3. Packaging and Internal C.

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MOSFETs Silicon N-channel MOS (U-MOS-H) TPN1200APL 1. Applications • High-Efficiency DC-DC Converters • Switching Voltage Regulators • Motor Drivers 2. Features (1) High-speed switching (2) Small gate charge: QSW = 7.5 nC (typ.) (3) Small output charge: Qoss = 24 nC (typ.) (4) Low drain-source on-resistance: RDS(ON) = 9.8 mΩ (typ.) (VGS = 10 V) (5) Low leakage current: IDSS = 10 µA (max) (VDS = 100 V) (6) Enhancement mode: Vth = 1.5 to 2.5 V (VDS = 10 V, ID = 0.3 mA) 3. Packaging and Internal Circuit TPN1200APL TSON Advance 1, 2, 3: Source 4: Gate 5, 6, 7, 8: Drain ©2017-2019 Toshiba Electronic Devices & Storage Corporation 1 Start of commercial production 2017-10 2019-10-18 Rev.2.0 TPN1200APL 4. Absolute Maximum Ratings (Note) (Ta = 25  unless otherwise specified) Characteristics Symbol Rating Unit Drain-source voltage Gate-source voltage VDSS 100 V VGSS ±20 Drain current (DC) (Tc = 25 ) (Note 1) ID 40 A Drain current (DC) (Silicon limit) (Note 1), (Note 2) 66 Drain current (pulsed) (t = 100 µs) (Note 1) IDP 160 Power dissipation (Tc = 25 ) PD 104 W Power dissipation (Note 3) 2.67 Power dissipation (Note 4) 0.63 Single-pulse avalanche energy (Note 5) EAS 39 mJ Single-pulse avalanche current Channel temperature (Note 5) IAS Tch 32 A 175  Storage temperature Tstg -55 to 175 Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc). 5. Thermal Characteristics Characteristics Channel-to-case thermal resistance (Tc = 25 ) Channel-to-ambient thermal resistance (Ta = 25 ) (Note 3) Channel-to-ambient thermal resistance (Ta = 25 ) (Note 4) Note 1: Ensure that the channel temperature does not exceed 175 . Note 2: Limited by silicon chip capability. Note 3: Device mounted on a glass-epoxy board (a), Figure 5.1 Note 4: Device mounted on a glass-epoxy board (b), Figure 5.2 Note 5: VDD = 60 V, Tch = 25  (initial), L = 42 µH, IAS = 32 A Symbol Rth(ch-c) Rth(ch-a) Rth(ch-a) Max Unit 1.43 /W 56 235 Fig. 5.1 Device Mounted on a Glass-Epoxy Board (a) Fig. 5.2 Device Mounted on a Glass-Epoxy Board (b) Note: This transistor is sensitive to electrostatic discharge and should be handled with care. ©2017-2019 Toshiba Electronic Devices & Storage Corporation 2 2019-10-18 Rev.2.0 TPN1200APL 6. Electrical Characteristics 6.1. Static Characteristics (Ta = 25  unless otherwise specified) Characteristics Symbol Test Condition Min Typ. Max Unit Gate leakage current IGSS VGS = ±16 V, VDS = 0 V   ±10 µA Drain cut-off current IDSS VDS = 100 V, VGS = 0 V   10 Drain-source breakdown voltage V(BR)DSS ID = 10 mA, VGS = 0 V 100   V Drain-source breakdown voltage (Note 6) V(BR)DSX ID = 10 mA, VGS = -20 V 65   Gate threshold voltage Vth VDS = 10 V, ID = 0.3 mA 1.5  2.5 Drain-source on-resistance RDS(ON) VGS = 4.5 V, ID = 14 A  13.3 20 mΩ VGS = 10 V, ID = 20 A  9.8 11.5 Note 6: If a reverse bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the drainsource breakdown voltage is lowered in this mode. 6.2. Dynamic Characteristics (Ta = 25  unless otherwise specified) Characteristics Input capacitance Reverse transfer capacitance Output capacitance Gate resistance Switching time (rise time) Switching time (turn-on time) Switching time (fall time) Switching time (turn-off time) Symbol Test Condition Ciss Crss Coss rg tr ton tf toff VDS = 50 V, VGS = 0 V, f = 1 MHz  See Fig. 6.2.1 Min Typ. Max Unit  1425 1855 pF  15 50  205   2.1 3.2 Ω  6  ns  19   6   34  VDD ≈ 50 V VGS = 0 V/ 10 V ID = 20 A RL = 2.5 Ω RGG = 4.7 Ω RGS = 4.7 Ω Duty ≤ 1 %, tw = 10 µs Fig. 6.2.1 Switching Time Test Circuit 6.3. Gate Charge Characteristics (Ta = 25  unless otherwise specified) Characteristics Total gate charge (gate-source plus gate-drain) Gate-source charge 1 Gate-drain charge Gate switch charge Output charge Symbol Test Condition Qg Qgs1 Qgd QSW Qoss VDD ≈ 50 V, VGS = 10 V, ID = 20 A VDD ≈ 50 V, VGS = 4.5 V, ID = 20 A VDD ≈ 50 V, VGS = 10 V, ID = 20 A VDS = 50 V, VGS = 0 V, f = 1 MHz Min Typ. Max Unit  24  nC  12   5.6   4.9   7.5   24  ©2017-2019 Toshiba Electronic Devices & Storage Corporation 3 2019-10-18 Rev.2.0 TPN1200APL 6.4..


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