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M15T2G16128A
DDR3 SDRAM
Description
ESMT (Preliminary) M15T2G16128A (2L) DDR3(L) SDRAM Feature Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V) ˗ SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V) JEDEC DDR3(L) Compliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) ˗ Double-data rate on DQs, DQS and DM Data Integrity ˗ Auto Self Refresh (ASR) by...
ESMT
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M15T2G16128A
DDR3 SDRAM
- ESMT
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