Mobile DDR SDRAM
ESMT
(Prliminary)
Mobile DDR SDRAM
Features
JEDEC Standard Internal pipelined double-data-rate architecture, two data...
Description
ESMT
(Prliminary)
Mobile DDR SDRAM
Features
JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) No DLL; CLK to DQS is not synchronized.
Differential clock inputs (CLK and CLK )
Four bank operation CAS Latency : 2, 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8, 16 Special function support - PASR (Partial Array Self Refresh) - Internal TCSR (Temperature Compensated Self
Refresh) - DS (Drive Strength) - Deep Power Down (DPD) Mode - Status Read Register (SRR)
M53D1G3232A
8M x 32Bit x 4 Banks
Mobile DDR SDRAM
All inputs except data & DM are sampled at the rising edge of the system clock(CLK) DQS is edge-aligned with data for READ; center-aligned with data for WRITE Data mask (DM) for write masking only VDD/VDDQ = 1.7V ~ 1.95V Auto & Self refresh 7.8us refresh interval (64ms refresh period, 8K cycle) LVCMOS-compatible inputs
Ordering Information
Product ID M53D1G3232A-5BG M53D1G3232A-6BG M53D...
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