M53D5121632A

ESMT Mobile DDR SDRAM Features JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) No DLL; CLK to DQS is not synchronized. Differential clock inputs (CLK and CLK ) Four bank operation CAS Latency : 2, 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8, 16 Special function support - PASR (Partial Array Self Refresh) - Internal TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength) - Deep Power Down (DPD) Mode M53D5121632A 8M x16 Bit x 4 Banks Mobile DDR SDRAM All inputs except data & DM are sampled at the rising edge of the system clock(CLK) DQS is edge-aligned with data for READ; center-aligned with data for WRITE Data mask (DM) for write masking only VDD/VDDQ = 1.7V ~ 1.95V Auto & Self refresh 7.8us refresh interval (64ms refresh period, 8K cycle) LVCMOS-compatible inputs Ordering Information Product ID M53D5121632A -5BG M53D5121632A -6BG M53D5121632A -7.5BG Max Freq. 200MHz 166MHz...