STP5950

STP5950 P Channel Enhancement Mode MOSFET -35.0A DESCRIPTION STP5950 is the P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These device is particularly suited for low voltage application, notebook computer power management and other battery circuits where high-side switching. PIN CONFIGURATION FEATURE l -100V/-15A, RDS(ON) = 36mΩ (Typ.) @VGS = -10V l -100V/-10A, RDS(ON) = 40mΩ @VGS = -4.5V l Super high density cell design for extremely low RDS(ON) l Exceptional on-resistance and maximum DC current capability l TO-220 package design ABSOULTE MAXIMUM RATINGS (Ta = 25℃ Unless otherwise noted ) Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (TJ=150℃) Pulsed Drain Current Power Dissipation TA=25℃ TA=80℃ TA=25℃ Operation Junction Temperature Storgae Temperature Range Thermal Res...