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ODCXXX01

CMOS Gate Array

Description

2'&;;;[[ ® $0,+* PLFURQ &026 *DWH $UUD\ Description ODCXXXxx is a family of 1 to 24 mA, non-inverting, CMOS-level output buffer pieces. Logic Symbol Truth Table ODCXXXxx A PADM A PADM LL HH HDL Syntax Verilog .................... ODCXXXxx inst_name (PADM, A); VHDL...................... inst_name: ODCXXXxx port map (PADM, A); Pin Loading Pin Na...

AMI

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