CMOS Gate Array
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$0,+* PLFURQ &026 *DWH $UUD\
Description ODCXIPxx is a family of 1 to 8 mA, inverting, CMOS-level, out...
Description
2'&;,3[[
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$0,+* PLFURQ &026 *DWH $UUD\
Description ODCXIPxx is a family of 1 to 8 mA, inverting, CMOS-level, output buffer pieces with P-channel, open-drains (pull-up).
Logic Symbol
Truth Table
ODCXIPxx A
PADM
A PADM LH HZ Z = High Impedance
HDL Syntax Verilog .................... ODCXIPxx inst_name (PADM, A); VHDL...................... inst_name: ODCXIPxx port map (PADM, A);
Pin Loading
Pin Name A (eq-load) PADM (pF)
ODCXIP01 2.8 4.92
Load
ODCXIP02
ODCXIP04
2.8 2.8
4.92 4.92
ODCXIP08 3.9 4.93
Power Characteristics
Cell Output Drive (mA)
ODCXIP01
1
ODCXIP02
2
ODCXIP04
4
ODCXIP08
8
a. See page 2-15 for power equation.
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
TBD
148.8
TBD
153.6
TBD
162.0
TBD
178.9
Pad Logic
4-21
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$0,+* PLFURQ &026 *DWH $UUD\
Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
ODCXIP01
Capacitive Load (pF)
From: A To: PADM
tZH
15 4.73
ODCXIP02
Capacitiv...
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