TD02

Core Logic 7'[ $0,+*  PLFURQ &026 *DWH $UUD\ Description TD0x is a family of non-inverting time delays. Logic Symbol Truth Table TD0x Delay AQ LL HH HDL Syntax Verilog .................... TD0x inst_name (Q, A); VHDL...................... inst_name: TD0x port map (Q, A); Pin Loading Pin Name A TD02 1.5 Equivalent Loads TD03 1.0 TD08 1.0 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) TD02 9.0 TBD 20.9 TD03 9.0 TBD 22.8 TD08 17.0 TBD 48.4 a. See page 2-15 for power equation. ® 3-236 7'[ ® Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Number of Equivalent Loads 1 TD02 From: A To: Q tPLH tPHL 2.62 2.73 Number of Equivalent Loads 1 TD03 From: A To: Q tPLH tPHL 4.01 4.12 Number of Equivalent Loads 1 TD08 From: A To: Q tPLH tPHL 11.98 11.49 8 2.71 2.88 8 4.05 4.15 8 12.11 11.54 $0,+*  PLFURQ &026 *DWH $UUD\ 15 2.80 2.96 15...