CMOS Gate Array
Core Logic
1$[
®
$0,+* PLFURQ &026 *DWH $UUD\
Description NA6x is a family of 6-input gates which perform the l...
Description
Core Logic
1$[
®
$0,+* PLFURQ &026 *DWH $UUD\
Description NA6x is a family of 6-input gates which perform the logical NAND function.
Logic Symbol
NA6x
A B C D E F
A B C D E F
Q Q
Truth Table A BCDE F LXXXXX XLXXXX XXLXXX XXXLXX XXXXLX XXXXXL HHHHHH
Q H H H H H H L
HDL Syntax Verilog .................... NA6x inst_name (Q, A, B, C, D, E, F); VHDL...................... inst_name: NA6x port map (Q, A, B, C, D, E, F);
Pin Loading
Pin Name
A B C D E F
NA61 1.0 1.0 1.0 1.0 1.0 1.0
NA62 2.1 2.1 2.1 2.1 2.1 2.1
Equivalent Loads NA63 2.1 2.1 2.1 2.1 2.1 2.1
NA64 2.1 2.1 2.1 2.1 2.1 2.1
NA66 2.1 2.1 2.1 2.1 2.1 2.1
3-167
Core Logic
1$[
$0,+* PLFURQ &026 *DWH $UUD\
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
NA61
5.0
TBD
8.7
NA62
9.0
TBD
14.7
NA63
12.0
TBD
18.6
NA64
12.0
TBD
19.0
NA66
11.0
TBD
20.0
a. See page 2-15 for power equation.
Propagation Delays (ns)
Cond...
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