DF412

')[ ® $0,+*  PLFURQ &026 *DWH $UUD\ Description DF41x is a family of static, master-slave, multiplexed scan D flip-flops. RESET is asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock. Logic Symbol DF41x D C SD SE R Q Q Truth Table C D RN SD SE Q QN ↑HHX LHL ↑LHXL LH ↑ XHHHH L ↑XHLHLH XXLXXLH L X H X X NC NC NC = No Change Core Logic HDL Syntax Verilog .................... DF41x inst_name (Q, QN, C, D, RN, SD, SE); VHDL...................... inst_name: DF41x port map (Q, QN, C, D, RN, SD, SE); Pin Loading Pin Name C D RN SD SE DF411 1.0 1.0 1.0 1.0 2.1 Equivalent Loads DF412 DF414 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 2.1 2.2 DF416 1.0 1.0 1.0 1.0 2.2 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) DF411 12.0 TBD 25.6 DF412 13.0 TBD 28.8 DF414 17.0 TBD 34.8 DF416 19.0 TBD 47.6 3-83 Core Logic ')[ ® $0,+*  PL...