')[
®
$0,+* PLFURQ &026 *DWH $UUD\
Description
DF40x is a family of static, master-slave, multiplexed scan D flip-flops. SET is asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock.
Logic Symbol DF40x
DS C SD SE
Q Q
Truth Table C D SD SE SN Q QN ↑HX LHHL ↑LXLHLH ↑ XHHHH L ↑X LHHLH XXXXLHL L X X X H NC NC NC = No Change
Core Logic
HDL Syntax Verilog DF40x inst_name (Q, QN, C, D, SD, SE, SN); VHDL.