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BST84 Dataheets PDF



Part Number BST84
Manufacturers NXP
Logo NXP
Description N-channel transistor
Datasheet BST84 DatasheetBST84 Datasheet (PDF)

DISCRETE SEMICONDUCTORS DATA SHEET BST84 N-channel enhancement mode vertical D-MOS transistor Product specification File under Discrete Semiconductors, SC13b April 1995 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor DESCRIPTION N-channel vertical D-MOS transistor in SOT89 envelope and designed for use as line current interrupter in telephone sets and for application in relay, high-speed and line-transformer drivers. FEATURES • Direct interfac.

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DISCRETE SEMICONDUCTORS DATA SHEET BST84 N-channel enhancement mode vertical D-MOS transistor Product specification File under Discrete Semiconductors, SC13b April 1995 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor DESCRIPTION N-channel vertical D-MOS transistor in SOT89 envelope and designed for use as line current interrupter in telephone sets and for application in relay, high-speed and line-transformer drivers. FEATURES • Direct interface to C-MOS, TTL, etc. • High-speed switching • No second breakdown PINNING - SOT89 1 = source 2 = gate 3 = drain Transfer admittance ID = 250 mA; VDS = 15 V  Yfs typ. QUICK REFERENCE DATA Drain-source voltage Gate-source voltage (open drain) Drain current (DC) Total power dissipation up to Tamb = 25 °C Drain-source ON-resistance ID = 250 mA; VGS = 10 V RDS(on) typ. max. VDS ±VGSO ID Ptot max. max. max. max. BST84 200 V 20 V 250 mA 1 W 6 Ω 12 Ω 250 mS PIN CONFIGURATION handbook, halfpage handbook, 2 columns d g MBB076 - 1 s 1 Bottom view 3 2 MSB013 Marking: KN Fig.1 Simplified outline and symbol. April 1995 2 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Drain-source voltage Gate-source voltage (open drain) Drain current (DC) Drain current (peak) Total power dissipation up to Tamb = 25 °C (note 1) Storage temperature range Junction temperature THERMAL RESISTANCE From junction to ambient (note 1) Note 1. Transistor mounted on a ceramic substrate with area of 2.5 cm2 and thickness of 0.7 mm. Rth j-a = 125 K/W VDS ±VGSO ID IDM Ptot Tstg Tj max. max. max. max. max. max. 200 V 20 V 250 mA 800 mA 1 W 150 °C BST84 −65 to + 150 °C April 1995 3 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor CHARACTERISTICS Tj = 25 °C unless otherwise specified Drain-source breakdown voltage ID = 100 µA; VGS = 0 Drain-source leakage current VDS = 160 V; VGS = 0 Gate-source leakage current VGS = 20 V; VDS = 0 Gate threshold voltage ID = 1 mA; VDS = VGS Drain-source ON-resistance ID = 250 mA; VGS = 10 V Transfer admittance ID = 250 mA; VDS = 15 V Input capacitance at f = 1 MHz VDS = 10 V; VGS = 0 Output capacitance at f = 1 MHz VDS = 10 V; VGS = 0 Feedback capacitance at f = 1 MHz VDS = 10 V; VGS = 0 Switching times (see Figs 2 and 3) ID = 250 mA; VDD = 50 V; VGS = 0 to 10 V ton typ. max. typ. max. 4 ns 10 ns 15 ns 25 ns Crss typ. max. 5 pF 10 pF Coss typ. max. 20 pF 30 pF Ciss typ. max. 70 pF 90 pF  Yfs typ. 250 mS RDS(on) typ. max. VGS(th) min. max. 0.8 V 2.8 V 6 Ω 12 Ω IGSS max. 100 nA IDSS max. 10 µA V(BR)DSS min. 200 V BST84 toff April 1995 4 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BST84 handbook, halfpage VDD = 50 V handbook, halfpage 90 % INPUT 10 % 90 % 10 V 0V ID 50 Ω MBB691 OUTPUT 10 % ton toff MBB692 Fig.2 Switching times test circuit. Fig.3 Input and output waveforms. 103 handbook, halfpage MDA764 VGS = 10 V 4V 5V handbook, halfpage 1 MDA765 ID (mA) ID (A) 0.8 0.6 102 0.4 0.2 10 0 4 6 8 10 12 14 RDSon (Ω) 0 2 4 6 8 10 VGS (V) Fig.4 Tj = 25 °C; typical values. Fig.5 Tj = 25 °C; VDS = 10 V; typical values. April 1995 5 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BST84 handbook, halfpage 1 MDA766 ID (A) 0.8 VGS = 10 V 5V handbook, halfpage 1.2 MDA767 Ptot (W) 0.8 0.6 4V 0.4 0.4 0.2 3V 0 0 2 4 6 8 10 VDS (V) 0 0 50 100 150 200 Tamb (°C) Fig.6 Tj = 25 °C; typical values. Fig.7 Power derating curve. handbook, halfpage 3 MDA742 handbook, halfpage 1.2 k MDA743 k 2.5 1.1 2 1 1.5 0.9 1 0.8 0.5 −50 0 50 100 Tj (°C) 150 0.7 −50 0 50 100 Tj (°C) 150 Fig.8 R DS (on) at T j k = ------------------------------------------- ; R DS (on) at 25 ° C at 400 mA/10 V; typical values. Fig.9 V GS ( th ) at T j -; k = -------------------------------------------V GS ( th ) at 25 ° C VGS(th) at 1 mA; typical values. April 1995 6 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BST84 handbook, halfpage 120 MDA768 C (pF) 80 Ciss 40 Coss Crss 0 0 10 20 VDS (V) 30 Fig.10 Tj = 25 °C; VGS = 0; f = 1 MHz; typical values. April 1995 7 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor PACKAGE OUTLINES Plastic surface mounted package; collector pad for good heat transfer; 3 leads BST84 SOT89 D B A b3 E HE L 1 2 b2 3 c w M b1 e1 e 0 2 scale 4 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.6 1.4 b1 0.48 0.35 b2 0.53 0.40 b3 1.8 1.4 c 0.44 0.37 D 4.6 4.4 E 2.6 2.4 e 3.0 e1 1.5 HE 4.25 3.75 L min. 0.8 w 0.13 OUTLINE VERSION SOT89 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-02-28 April 1995 8 Philips Semiconductors Produc.


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