Document
DISCRETE SEMICONDUCTORS
DATA SHEET
BSP110 N-channel enhancement mode vertical D-MOS transistor
Product specification File under Discrete Semiconductors, SC13b April 1995
Philips Semiconductors
Product specification
N-channel enhancement mode vertical D-MOS transistor
DESCRIPTION N-channel enhancement mode vertical D-MOS transistor in a miniature SOT223 envelope and designed for use in telephone ringer circuits and for application in relay, high-speed and line transformer drivers. FEATURES • Direct interface to C-MOS, TTL, etc. • High-speed switching • No secondary breakdown PINNING - SOT223 1 = gate 2 = drain 3 = source 4 = drain MARKING CODE BSP110 PIN CONFIGURATION QUICK REFERENCE DATA Drain-source voltage Drain source voltage (non-repetitive peak; tp ≤ 2 ms) Gate-source voltage (open drain) Drain current (DC) Total power dissipation up to Tamb = 25 °C Drain-source ON-resistance ID = 200 mA; VGS = 10 V Transfer admittance ID = 200 mA; VDS = 15 V Yfs min. typ. RDS(on) VDS(SM) ± VGSO ID Ptot VDS
BSP110
max. max. max. max. max. typ. max.
80 V 100 V 20 V 325 mA 1.5 W 4.5 Ω 7 Ω 75 mS 150 mS
handbook, halfpage
4
d
g
1 Top view
2
3
MAM054
s
Fig.1 Simplfied outline and symbol.
April 1995
2
Philips Semiconductors
Product specification
N-channel enhancement mode vertical D-MOS transistor
RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Drain-source voltage Drain-source voltage (non-repetitive peak; tp ≤ 2 ms) Gate-source voltage (open drain) Drain current (DC) Drain current (peak) Total power dissipation up to Tamb = 25 °C (note 1) Storage temperature range Junction temperature THERMAL RESISTANCE From junction to ambient (note 1) Note Rth j-a = VDS(SM) ± VGSO ID IDM Ptot Tstg Tj max. max. max. max. max. max. VDS max.
BSP110
80 V 100 V 20 V 325 mA 650 mA 1.5 W 150 °C
−65 to + 150 °C
83.3 K/W
1. Device mounted on an epoxy printed-circuit board 40 mm × 40 mm × 1.5 mm; mounting pad for the drain lead min. 6 cm2. CHARACTERISTICS Tj = 25 °C unless otherwise specified Drain-source breakdown voltage ID = 10 µA; VGS = 0 Drain-source leakage current VDS = 60 V; VGS = 0 Gate-source leakage current VGS = 20 V; VDS = 0 Gate threshold voltage ID = 1 mA; VDS = VGS Drain-source ON-resistance (see Fig.4) ID = 150 mA; VGS = 5 V RDS(on) typ. max. typ. max. min. typ. IGS(th) min. max. 0.8 V 2.8 V 7 Ω 10 Ω 4.5 Ω 7 Ω 75 mS 150 mS IGSS max. 100 nA IDSS max. 1.0 µA V(BR) DSS min. 80 V
ID = 200 mA; VGS = 10 V Transfer admittance ID = 200 mA; VDS = 5 V Input capacitance at f = 1 MHz; VDS = 10 V; VGS = 0
RDS(on)
| Yfs|
Ciss
typ. max.
15 pF 30 pF
April 1995
3
Philips Semiconductors
Product specification
N-channel enhancement mode vertical D-MOS transistor
Output capacitance at f = 1 MHz; VDS = 10 V; VGS = 0 Feedback capacitance at f = 1 MHz; VDS = 10 V; VGS = 0 Switching times (see Figs 2 and 3) ID = 200 mA; VDD = 50 V; VGS = 0 to 10 V ton typ. max. typ. max. Crss typ. max. Coss typ. max.
BSP110
13 pF 20 pF
3 p.