Document
Philips Semiconductors
Product specification
TrenchMOS™ transistor Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mounting. Using ’trench’ technology the device features very low on-state resistance and has integral zener diodes giving ESD protection up to 2kV. It is intended for use in automotive and general purpose switching applications.
BUK9628-55
QUICK REFERENCE DATA
SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V MAX. 55 40 96 175 28 UNIT V A W ˚C mΩ
PINNING - SOT404
PIN 1 2 3 mb gate drain source drain DESCRIPTION
PIN CONFIGURATION
mb
SYMBOL
d
g
2 1 3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR ±VGS ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 55 55 10 40 28 160 96 175 UNIT V V V A A A W ˚C
ESD LIMITING VALUE
SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage, all pins CONDITIONS Human body model (100 pF, 1.5 kΩ) MIN. MAX. 2 UNIT kV
THERMAL RESISTANCES
SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS Minimum footprint, FR4 board TYP. 50 MAX. 1.56 UNIT K/W K/W
April 1998
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor Logic level FET
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IGSS ±V(BR)GSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Gate source leakage current Gate-source breakdown voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C VDS = 55 V; VGS = 0 V; VGS = ±5 V; VDS = 0 V IG = ±1 mA; VGS = 5 V; ID = 20 A Tj = 175˚C Tj = 175˚C Tj = 175˚C MIN. 55 50 1 0.5 10 TYP. 1.5 0.05 0.02 22 -
BUK9628-55
MAX. 2 2.3 10 500 1 10 28 59
UNIT V V V V µA µA µA µA V mΩ mΩ
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified SYMBOL gfs Ciss Coss Crss td on tr td off tf Ld Ls PARAMETER Forward transconductance Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance CONDITIONS VDS = 25 V; ID = 25 A VGS = 0 V; VDS = 25 V; f = 1 MHz MIN. 13 TYP. 1300 250 130 22 85 70 64 2.5 7.5 MAX. 1700 300 180 32 125 95 85 UNIT S pF pF pF ns ns ns ns nH nH
VDD = 30 V; ID = 25 A; VGS = 5 V; RG = 10 Ω Resistive load Measured from upper edge of drain tab to centre of die Measured from source lead soldering point to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 40 A; VGS = 0 V IF = 40 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 30 V TYP. 0.95 1.0 41 0.16 MAX. 40 160 1.2 UNIT A A V ns µC
April 1998
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL WDSS PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 35 A; VDD ≤ 25 V; VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C MIN. TYP. -
BUK9628-55
MAX. 70
UNIT mJ
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
1000 ID/A RDS(ON) = VDS/ID tp = 1 us 10us 100 us 1 ms 10ms 100ms
100
DC 10
0
20
40
60
80 100 Tmb / C
120
140
160
180
1
1
10
VDS/V
100
Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
Normalised Current Derating
Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp
Zth/ (K/W)
120 110 100 90 80 70 60 50 40 30 20 10 0
ID%
10
1
0.5 0.2 0.1 P D tp D= tp T t
0.1
0.05 0.02 T
0
0
20
40
60
80 100 Tmb / C
120
140
160
180
0.01
1.0E-06
0.0001
0.01 t/s
1
100
Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
April 1998
3
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor Logic level FET
BUK9628-55
100 ID/A 80
10 8 6
5
VGS/V = 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0
40 gfs/S 35 30 25 20 15 10 5
60
40
20
0
0
2
4
VDS/V
6
8
2.8 2.6 2.4 2.2 2.0 10
0
10
20
30
40
ID/A
50
60
70
80
Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); param.