Document
Philips Semiconductors
Product specification
TrenchMOS™ transistor Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mounting Using ’trench’ technology the device features very low on-state resistance and has integral zener diodes giving ESD protection up to 2kV. It is intended for use in automotive and general purpose switching applications.
BUK9608-55
QUICK REFERENCE DATA
SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V MAX. 55 75 187 175 8 UNIT V A W ˚C mΩ
PINNING - SOT404
PIN 1 2 3 mb gate drain source drain DESCRIPTION
PIN CONFIGURATION
mb
SYMBOL
d
g
2 1 3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR ±VGS ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 55 55 10 75 65 240 187 175 UNIT V V V A A A W ˚C
ESD LIMITING VALUE
SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage CONDITIONS Human body model (100 pF, 1.5 kΩ) MIN. MAX. 2 UNIT kV
THERMAL RESISTANCES
SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS Minimum footprint,FR4 board TYP. 50 MAX. 0.8 UNIT K/W K/W
April 1998
1
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS™ transistor Logic level FET
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IGSS ±V(BR)GSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Gate source leakage current Gate-source breakdown voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C VDS = 55 V; VGS = 0 V; VGS = ±5 V; VDS = 0 V IG = ±1 mA; VGS = 5 V; ID = 25 A Tj = 175˚C Tj = 175˚C Tj = 175˚C MIN. 55 50 1.0 0.5 10 TYP. 1.5 0.05 0.02 6.5 -
BUK9608-55
MAX. 2.0 2.3 10 500 1 10 8 17
UNIT V V V V V µA uA µA µA V mΩ mΩ
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified SYMBOL gfs Ciss Coss Crss td on tr td off tf Ld Ls PARAMETER Forward transconductance Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance CONDITIONS VDS = 25 V; ID = 25 A VGS = 0 V; VDS = 25 V; f = 1 MHz MIN. 40 TYP. 90 5200 840 350 45 120 225 100 3.5 7.5 MAX. 6900 1000 480 60 170 300 135 UNIT S pF pF pF ns ns ns ns nH nH
VDD = 30 V; ID = 25 A; VGS = 5 V; RG = 10 Ω
Measured from upper edge of drain tab to centre of die Measured from source lead soldering point to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 75 A; VGS = 0 V IF = 75 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 30 V TYP. 0.85 1.0 65 0.18 MAX. 75 240 1.2 UNIT A A V V ns µC
April 1998
2
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS™ transistor Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL WDSS PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 75 A; VDD ≤ 25 V; VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C MIN. TYP. -
BUK9608-55
MAX. 500
UNIT mJ
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
BUKX508-55
1000
ID / A
RDS(ON) = VDS/ID 100
tp = 10 us 100 us 1 ms
10
DC
10 ms 100 ms
0
20
40
60
80 100 Tmb / C
120
140
160
180
1
1
10
VDS / V
100
Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
Normalised Current Derating
Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp
Zth / (K/W) 1E+00
120 110 100 90 80 70 60 50 40 30 20 10 0
ID%
0.5 1E-01 0.2 0.1 0.05 1E-02 0.02 0 1E-03 1E-07
P D
tp
D=
tp T t
T
0
20
40
60
80 100 Tmb / C
120
140
160
180
1E-05
1E-03 t/s
1E-01
1E+01
Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
April 1998
3
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS™ transistor Logic level FET
BUK9608-55
100 10 ID/A 80
3.4 4.0
VGS/V =
3.2
120 gfs/S 110 100 90
3.0 60 2.8 40 2.6 20 2.4 2.2 0 0 2 4 VDS/V 6 8 10
80 70 60 50 40 30 20 10 0 0 20 40 ID/A 60 80 100
Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS
Fig.8. Typi.