Philips Semiconductors
Product specification
TrenchMOS™ transistor Logic level FET
GENERAL DESCRIPTION
N-channel enhan...
Philips Semiconductors
Product specification
TrenchMOS™
transistor Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power
transistor in a plastic envelope using ’trench’ technology. The device features very low on-state resistance and has integral zener diodes giving ESD protection up to 2kV. It is intended for use in automotive and general purpose switching applications.
BUK9518-30
QUICK REFERENCE DATA
SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V MAX. 30 55 103 175 18 UNIT V A W ˚C mΩ
PINNING - TO220AB
PIN 1 2 3 tab gate drain source drain DESCRIPTION
PIN CONFIGURATION
tab
SYMBOL
d
g s
1 23
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR ±VGS ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 30 30 10 55 38 220 103 175 UNIT V V V A A A W ˚C
THERMAL RESISTANCES
SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS in free air TYP. 60 MAX. 1.45 UNIT K/W K/W
ESD LIMITING VALUE
SYMBOL VC PARAMETER Electrostatic discharge capac...