MPC5602P

Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5602P Rev. 6,12/2012 MPC5602P MPC5602P Microcontroller Data Sheet Up to 64 MHz, single issue, 32-bit CPU core complex (e200z0h) — Compliant with Power Architecture embedded category — Variable Length Encoding (VLE) Memory organization — Up to 256 KB on-chip code flash memory with ECC and erase/program controller — Optional: additional 64 (4 × 16) KB on-chip data flash memory with ECC for EEPROM emulation — Up to 20 KB on-chip SRAM with ECC Fail-safe protection — Programmable watchdog timer — Non-maskable interrupt — Fault collection unit Nexus Class 1 interface Interrupts and events — 16-channel eDMA controller — 16 priority level controller — Up to 25 external interrupts — PIT implements four 32-bit timers — 120 interrupts are routed via INTC General purpose I/Os — Individually programmable as input, output or special function — 37 on 64 LQFP — 64 on 100 LQFP 1 general purpose eTimer unit — 6 timers each with up/down capabilities — 16-bit resolution, cascadeable counters — Quadrature decode with rotation direction flag — Double buffer input capture and output compare Communications interfaces — Up to 2 LINFlex modules (1× Master/Slave, 1× Master only) — Up to 3 DSPI channels with automatic chip select generation (up to 8/4/4 chip selects) 100 LQFP (14 mm x 14 mm) 64 LQFP (10 mm x 10 mm) — 1 FlexCAN interface (2.0B Active) with 32 message buffers — 1 safety port based on FlexCAN wit...