Document
FUJITSU SEMICONDUCTOR DATA SHEET
FLASH MEMORY
CMOS
16M (2M × 8) BIT
DS05-20857-4E
MBM29LV017-80/-90/-12
s FEATURES
• Address specification is not necessary during command sequence • Single 3.0 V read, program and erase
Minimizes system level power requirements • Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts
40-pin TSOP (I) (Package suffix: PTN-Normal Bend Type, PTR-Reversed Bend Type) 48-ball FBGA (Package suffix: PBT) • Minimum 100,000 program/erase cycles • High performance 80 ns maximum access time • Sector erase architecture Uniform sectors of 64K bytes each Any combination of sectors can be concurrently erased. Also supports full chip erase • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector • Embedded programTM Algorithms Automatically programs and verifies data at specified address • Data Polling and Toggle Bit feature for detection o.