Document
FUJITSU SEMICONDUCTOR DATA SHEET
FLASH MEMORY
CMOS
1M (128K × 8) BIT
DS05-20861-3E
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
s FEATURES
• Single 3.0 V read, program, and erase Minimizes system level power requirements
• Compatible with JEDEC-standard commands Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts 32-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) 32-pin PLCC (Package suffix: PD)
• Minimum 100,000 program/erase cycles • High performance
55 ns maximum access time • Sector erase architecture
One 8K byte, two 4K bytes, and seven 16K bytes Any combination of sectors can be concurrently erased. Also supports full chip erase • Boot Code Sector Architecture T = Top sector B = Bottom sector • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address • Data Polling .