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M5M4V16169DTP-10 Dataheets PDF



Part Number M5M4V16169DTP-10
Manufacturers Mitsubishi
Logo Mitsubishi
Description 16M (1M-WORD BY 16-BIT) CACHED DRAM
Datasheet M5M4V16169DTP-10 DatasheetM5M4V16169DTP-10 Datasheet (PDF)

MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Preliminary This document is a preliminary Target Spec. and some of the contents are subject to change without notice. DESCRIPTION PINCONFIGURATION (TOP VIEW) 1. The M5M4V16169DTP/RT is a 16M-bit Cached DRAM which integrates input registers, a 1,048,576-word by 16-bit dynamic memory array and a 1024- word by 16-bit static RAM array as a Cache memory (block size 8x16) .

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MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Preliminary This document is a preliminary Target Spec. and some of the contents are subject to change without notice. DESCRIPTION PINCONFIGURATION (TOP VIEW) 1. The M5M4V16169DTP/RT is a 16M-bit Cached DRAM which integrates input registers, a 1,048,576-word by 16-bit dynamic memory array and a 1024- word by 16-bit static RAM array as a Cache memory (block size 8x16) onto a single monolithic circuit. The block data transfer between the DRAM and the data transfer buffers (RB1/RB2/WB1/WB2) is performed in one instruction cycle, a fundamental advantage over a conventional DRAM/SRAM cache. The RAM is fabricated with a high performance CMOS process, and is ideal for 2. large-capacity memory systems where high speed, low power dissipation, and low cost are essential. The use of quadruple-layer polysilicon process combined Vcc DQCl DQCu CC1# CC0# WE# CS# CMd# CMs#.


M5M4V16169DTP-8 M5M4V16169DTP-10 M5M4V16169DTP-15


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