CAT28LV65

Preliminary CAT28LV65 64K-Bit CMOS PARALLEL E2PROM FEATURES s 3.0V to 3.6V Supply s Read Access Times: s CMOS and TTL Compatible I/O s Automatic Page Write Operation: – 250/300/350ns s Low Power CMOS Dissipation: – 1 to 32 Bytes in 5ms – Page Load Timer s End of Write Detection: – Active: 8 mA Max. – Standby: 100 µA Max. s Simple Write Operation: – On-Chip Address and Data Latches – Self-Timed Write Cycle with Auto-Clear s Fast Write Cycle Time: – Toggle Bit – DATA Polling – RDY/BUSY s Hardware and Software Write Protection s 100,000 Program/Erase Cycles s 100 Year Data Retention – 5ms Max. s Commercial, Industrial and Automotive Temperature Ranges DESCRIPTION The CAT28LV65 is a low voltage, low power, CMOS parallel E2PROM organized as 8K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling, RDY/BUSY and Toggle status bit signal the start and end of the self-timed write cycle. Additionally, the CAT28LV65 features hardware and software write protection. The CAT28LV65 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32pin PLCC packages. BLOCK DIAGRAM A5–A12 ADDR. BUFFER & LATCHES INA...