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CAT25C33 Dataheets PDF



Part Number CAT25C33
Manufacturers Catalyst Semiconductor
Logo Catalyst Semiconductor
Description 2K/4K/8K/16K/32K SPI Serial CMOS E2PROM
Datasheet CAT25C33 DatasheetCAT25C33 Datasheet (PDF)

Advanced CAT25C03/05/09/17/33 2K/4K/8K/16K/32K SPI Serial CMOS E2PROM FEATURES s 10 MHz SPI Compatible s 1.8 to 6.0 Volt Operation s Hardware and Software Protection s Zero Standby Current s Low Power CMOS Technology s SPI Modes (0,0 &1,1) s Commercial, Industrial and Automotive s 1,000,000 Program/Erase Cycles s 100 Year Data Retention s Self-Timed Write Cycle s 8-Pin DIP/SOIC, 16-Pin SOIC and 14-Pin TSSOP s Page Write Buffer s Write Protection Temperature Ranges – Protect First Page, Last P.

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Advanced CAT25C03/05/09/17/33 2K/4K/8K/16K/32K SPI Serial CMOS E2PROM FEATURES s 10 MHz SPI Compatible s 1.8 to 6.0 Volt Operation s Hardware and Software Protection s Zero Standby Current s Low Power CMOS Technology s SPI Modes (0,0 &1,1) s Commercial, Industrial and Automotive s 1,000,000 Program/Erase Cycles s 100 Year Data Retention s Self-Timed Write Cycle s 8-Pin DIP/SOIC, 16-Pin SOIC and 14-Pin TSSOP s Page Write Buffer s Write Protection Temperature Ranges – Protect First Page, Last Page, Any 1/4 Array or Lower 1/2 Array DESCRIPTION The CAT25C03/05/09/17/33 is a 2K/4K/8K/16K/32K-Bit SPI Serial CMOS E2PROM internally organized as 256x8/512x8/1024x8/2048x8/4096x8 bits. Catalyst’s advanced CMOS Technology substantially reduces device power requirements. The CAT25C03/05 features a 16-byte page write buffer. The 25C09/17/33 features a 32-byte page write buffer.The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C03/05/09/17/33 is designed with software and hardware write protection features. The device is available in 8-pin DIP, 8-pin SOIC, 16-pin SOIC, 8-pin TSSOP and 14-pin TSSOP packages. PIN CONFIGURATION TSSOP Package (U14) SOIC Package (S16) SOIC Package (S) DIP Package (P) CS SO NC NC NC WP VSS TSSOP Package (U) 1 2 3 4 8 7 6 5 VCC HOLD SCL SI 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC HOLD NC NC NC SCK SI CS SO NC NC NC NC WP VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC HOLD NC NC NC NC SCK SI CS SO WP VSS 1 2 3 4 8 7 6 5 VCC CS HOLD SO SCK WP SI 1 2 3 4 VSS 8 7 6 5 VCC CS HOLD SO SCK SI WP VSS BLOCK DIAGRAM SENSE AMPS SHIFT REGISTERS PIN FUNCTIONS Pin Name SO SCK WP VCC VSS CS SI HOLD NC WORD ADDRESS BUFFERS COLUMN DECODERS Function Serial Data Output Serial Clock Write Protect +1.8V to +6.0V Power Supply Ground Chip Select Serial Data Input Suspends Serial Input No Connect STATUS REGISTER HIGH VOLTAGE/ TIMING CONTROL 25C128 F02 SO SI CS WP HOLD SCK I/O CONTROL SPI CONTROL LOGIC BLOCK PROTECT LOGIC CONTROL LOGIC XDEC E2PROM ARRAY DATA IN STORAGE © 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 25068-00 2/98 CAT25C03/05/09/17/33 Advanced ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. –55°C to +125°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to Ground(1) ............ –2.0V to +VCC +2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND (3) *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Parameter Endurance Data Retention ESD Susceptibility Latch-Up Min. 1,000,000 100 2000 100 Max. Units Cycles/Byte Years Volts mA Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 TDR(3) VZAP(3) ILTH(3)(4) D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Limits Symbol ICC1 ICC2 ISB ILI ILO VIL(3) VIH(3) VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Operating Write) Power Supply Current (Operating Read) Power Supply Current (Standby) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage VCC-0.2 VCC - 0.8 0.2 -1 VCC x 0.7 Min. Typ. Max. 5 0.4 0 2 3 VCC x 0.3 VCC + 0.5 0.4 Units mA mA µA µA µA V V V V V V 4.5V≤VCC<5.5V IOL = 3.0mA IOH = -1.6mA 1.8V≤VCC<2.7V IOL = 150µA IOH = -100µA VOUT = 0V to VCC, CS = 0V Test Conditions VCC = 5V @ 5MHz SO=open; CS=Vss VCC = 5.5V FCLK = 5MHz CS = VCC VIN = VSS or VCC Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. Doc. No. 25068-00 2/9.


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