AD9523-1

09278-001 Data Sheet Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs AD9523-1 FEATURES Output frequency: <1 MHz to 1 GHz Start-up frequency accuracy: <±100 ppm (determined by VCXO reference accuracy) Zero delay operation Input-to-output edge timing: <150 ps Dual VCO dividers 14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS 14 dedicated output dividers with jitter-free adjustable delay Adjustable delay: 63 resolution steps of ½ period of VCO output divider Output-to-output skew: <50 ps Duty cycle correction for odd divider settings Automatic synchronization of all outputs on power-up Absolute output jitter: <150 fs at 122.88 MHz Integration range: 12 kHz to 20 MHz Broadband timing jitter: 124 fs Digital lock detect Nonvolatile EEPROM stores configuration settings SPI- and I²C-compatible serial control port Dual PLL architecture PLL1 Low bandwidth for reference input clock cleanup with external VCXO Phase detector rate up to 130 MHz Redundant reference ...