MT40A512M8

4Gb: x8, x16 Automotive DDR4 SDRAM Features Automotive DDR4 SDRAM MT40A512M8 MT40A256M16 Features VDD = VDDQ = 1.2V ±60mV VPP = 2.5V –125mV/+250mV On-die, internal, adjustable VREFDQ generation 1.2V pseudo open-drain I/O Refresh maximum interval time at TC temperature range: – 64ms at –40°C to 85°C – 32ms at 85°C to 95°C – 16ms at 96°C to 105°C – 8ms at 106°C to 125°C 16 internal banks ( x8): 4 groups of 4 banks each 8 internal banks (x16): 2 groups of 4 banks each 8n-bit prefetch architecture Programmable data strobe preambles Data strobe preamble training Command/Address latency (CAL) Multipurpose register read and write capability Write leveling Self refresh mode Low-power auto self refresh (LPASR) Temperature controlled refresh (TCR) Fine granularity refresh Self refresh abort Maximum power saving Output driver calibration Nominal, park, and dynamic on-die termination (ODT) Data bus inversion (DBI) for data bus Command/Address (CA) parity Databus write cyclic redundancy check (CRC) Per-DRAM addressability Connectivity test Hard post package repair (hPPR) and soft post package repair (sPPR) modes JEDEC JESD-79-4 compliant AEC-Q100 PPAP submission Options1 Configuration – 512 Meg x 8 – 256 Meg x 16 BGA package (Pb-free) – x8 – 78-ball (9mm x 10.5mm) – Rev. B – 78-ball (7.5mm x 11mm) – Rev. F FBGA package (Pb-free) – x16 – 96-ball (9mm x 14mm) – Rev. B – 96-ball (7.5mm x 13.5mm) – Rev. F Timing – cycle t...