DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
The SN54/ 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together.
LOGIC DIAGRAM
SET (SD) 5(11)
CLEAR...
