MC10210

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual 3-Input/3-Output OR Gate The MC10210 is designed to drive up to six transmission lines simul– taneously. The multiple outputs of this device also allow the wire “OR” –ing of several levels of gating for minimization of gate and package count. The ability to control three parallel lines with minimum propagation delay from a single point makes the MC10210 particularly useful in clock distribution applications where minimum clock skew is desired. PD = 160 mW typ/pkg (No Loads) tpd = 1.5 ns typ (All Output Loaded) tr, tf = 1.5 ns typ (20%–80%) LOGIC DIAGRAM 5 6 7 9 10 11 VCC1 = PIN 1, 15 VCC2 = PIN 16 VEE = PIN 8 2 3 4 12 13 14 MC10210 L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 FN SUFFIX PLCC CASE 775–02 DIP PIN ASSIGNMENT VCC1 AOUT AOUT AOUT AIN AIN AIN VEE 1 2 3 4 5 6 7 8 16 VCC2 15 VCC1 14 BOUT 13 BOUT 12 BOUT 11 BIN 10 BIN 9 BIN Pin assignment is for Dual–in–Line Package. For PLCC pi...