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CD4021BMS Dataheets PDF



Part Number CD4021BMS
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description CMOS 8-Stage Static Shift Registers
Datasheet CD4021BMS DatasheetCD4021BMS Datasheet (PDF)

CD4014BMS, CD4021BMS December 1992 CMOS 8-Stage Static Shift Registers Description CD4014BMS -Synchronous Parallel or Serial Input/Serial Output CD4021BMS -Asynchronous Parallel Input or Synchronous Serial Input/Serial Output CD4014BMS and CD4021BMS series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel “JAM” inputs to each register stage. Each register stage is a D-ty.

  CD4021BMS   CD4021BMS


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CD4014BMS, CD4021BMS December 1992 CMOS 8-Stage Static Shift Registers Description CD4014BMS -Synchronous Parallel or Serial Input/Serial Output CD4021BMS -Asynchronous Parallel Input or Synchronous Serial Input/Serial Output CD4014BMS and CD4021BMS series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel “JAM” inputs to each register stage. Each register stage is a D-type, master-slave flip-flop. In addition to an output from stage 8, “Q” outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition in the CD4014BMS. In the CD4021BMS serial entry is synchronous with the clock but parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/ SERIAL CONTROL input is high, data is jammed into the 8stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021BMS, the CLOCK input of the internal stage is “forced” when asynchronous parallel entry is made. Register expansion using multiple packages is permitted. The CD4014BMS and CD4021BMS are supplied in these 16 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4T H1F H6W Features • High Voltage Types (20V Rating) • Medium Speed Operation 12MHz (Typ.) Clock Rate at VDD-VSS = 10V • Fully Static Operation • 8 Master-Slave Flip-Flops Plus Output Buffering and Control Gating • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Full Package Temperature Range) • 1V at VDD = 5V • 2V at VDD = 10V • 2.5V at VDD = 15V • Standardized Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of `B' Series CMOS Devices Applications: • Parallel Input/Serial Output Data Queueing • Parallel to Serial Data Conversion • General Purpose Register Pinout PI-8 1 Q6 2 Q8 3 PI-4 4 PI-3 5 PI-2 6 PI-1 7 VSS 8 16 VDD 15 PI-7 14 PI-6 13 PI-5 12 Q7 11 SERIAL IN Functional Diagram PAR. IN VDD 1 2 3 4 5 6 7 8 7 6 5 4 13 14 15 1 16 PARALLEL/SERIAL CONTROL SERIAL IN 9 11 10 2 12 3 10 CLOCK BUFFERED OUT 9 PARALLEL/SERIAL CONTROL CLOCK Q6 Q7 Q8 8 VSS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 3294 7-80 Specifications CD4014BMS, CD4021BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD.


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