Document
SO8N (150 mil width)
WLCSP8 (3.556 × 2.011 mm)
Product status link M95M02-DR M95M02-DF
M95M02-DR M95M02-DF
Datasheet
2-Mbit serial SPI bus EEPROM
Features
Compatible with the serial peripheral interface (SPI) bus Memory array • 2 Mbits (256 Kbytes) of EEPROM • Page size: 256 bytes • Write protection by block: ¼, ½, or whole memory • Additional write lockable page (identification page) Write • Byte write within 10 ms • Page write within 10 ms Clock frequency: 5 MHz Single supply voltage • 1.7 to 5.5 V over -20 °C to +85 °C • 1.8 to 5.5 V over -40 °C to +85 °C Operating temperature range • From -40 °C up to +85 °C Enhanced ESD protection More than 4 million write cycles More than 200-year data retention Packages • ECOPACK2 (RoHS compliant and halogen-free ) packages:
– SO8N – WLCSP8
DS7024 - Rev 13 - October 2022 For further information contact your local STMicroelectronics sales office.
www.st.com
M95M02-DR M95M02-DF
Description
1
Description
The M95M02 devices are electrically erasable programmable memory (EEPROM) organized as 262144 x 8 bits, accessed through the SPI bus.
Over an ambient temperature range of -40 °C / +85 °C the M95M02-DR can operate with a supply voltage from 1.8 to 5.5 V. Over an ambient temperature range of -20 °C / +85 °C the M95M02-DF can operate with a supply voltage from 1.7 to 5.5 V.
The M95M02 devices offer an additional page, named the Identification page (256 bytes). The Identification page can be used to store sensitive application parameters that can be (later) permanently locked in read-only mode.
Figure 1. Logic diagram
VCC
D C S W HOLD
M95xxx
Q
VSS
MS45413V1
The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is selected when chip select (S) is driven low. Communications with the device can be interrupted when the HOLD is driven low.
C D Q S W HOLD VCC VSS
Signal name
Table 1. Signal names
Serial clock Serial data input Serial data output Chip select Write protect Hold Supply voltage
Function
Ground
Input Input Output Input Input Input -
Direction
DS7024 - Rev 13
page 2/45
M95M02-DR M95M02-DF
Description
Figure 2. 8-pin package connections (top view)
M95xxx
S1 Q2 W3 VSS 4
8
VCC
7 HOLD
6C
5D
MS51579V1
1. See Section 10 Package information for package dimensions, and how to identify pin 1.
43
Figure 3. WLCSP connections
21
12
A
A
B
B
34
C
C
D
D
Bump side view
Top view (bumps underneath)
MS38243V1
1. See Section 10 Package information for package dimensions, and how to identify pin 1.
Position 1 2 3 4
Table 2. Signals vs. bump position
A
B
C
D
-
-
C
-
VCC
HOLD
-
D
S
-
-
VSS
-
Q
W
-
DS7024 - Rev 13
page 3/45
M95M02-DR M95M02-DF
Block diagram
2
Block diagram
The block diagram is organized as shown in the following figure.
Figure 4. Block diagram
S Q W
I/Os D C HOLD
Data register and ECC
Status register
Control logic
Sense amplifiers Page latches
Array
Identification page HV generator and sequencer
Y decode.