CMOS 8-Stage Presettable Synchronous Down Counters
Description
CD40102BMS CD40103BMS
December 1992
CMOS 8-Stage Presettable Synchronous Down Counters
Description
CD40102BMS and CD40103BMS consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102BMS is configured as two cascaded 4-bit BCD counters, and the CD40103BMS contains a single 8-bit binary cou...
